Tim Northover 03eecdccff FastISel: constrain the RegClass of operands when emitting instructions. ...

ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.

More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206283 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-15 13:59:49 +00:00

..

llvm

FastISel: constrain the RegClass of operands when emitting instructions.

2014-04-15 13:59:49 +00:00

llvm-c

Teach llvm-lto to respect the given RelocModel.

2014-04-14 13:54:16 +00:00