Javed Absar 172d6c078b [ARM]: Assign cost of scaling used in addressing mode for ARM cores ...

This patch assigns cost of the scaling used in addressing.
On many ARM cores, a negated register offset takes longer than a
non-negated register offset, in a register-offset addressing mode.

For instance:

LDR R0, [R1, R2 LSL #2]
LDR R0, [R1, -R2 LSL #2]

Above, (1) takes less cycles than (2).

By assigning appropriate scaling factor cost, we enable the LLVM
to make the right trade-offs in the optimization and code-selection phase.

Differential Revision: http://reviews.llvm.org/D24857

Reviewers: jmolloy, rengolin




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284127 91177308-0d34-0410-b5e6-96231b3b80d8

2016-10-13 14:57:43 +00:00

..

AArch64

[AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit load

2016-10-13 01:01:23 +00:00

AMDGPU

AMDGPU: Assume spilling will occur at -O0

2016-10-13 13:10:00 +00:00

ARM

[ARM]: Assign cost of scaling used in addressing mode for ARM cores

2016-10-13 14:57:43 +00:00

AVR

[RegAllocGreedy] Attempt to split unspillable live intervals

2016-10-11 01:04:36 +00:00

BPF

Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."

2016-09-28 16:37:50 +00:00

Generic

llc: Add -start-before/-stop-before options

2016-09-23 21:46:02 +00:00

Hexagon

Handle lane masks in LivePhysRegs when adding live-ins

2016-10-12 22:53:41 +00:00

Inputs

…

Lanai

Add a REQUIRES: assert on a Lanai test that uses a -debug-only flag

2016-07-29 19:35:22 +00:00

Mips

[mips][fastisel] Consider soft-float an unsupported floating point mode

2016-10-04 10:35:07 +00:00

MIR

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

MSP430

[SelectionDAGBuilder] Support llvm.flt.rounds on targets where i32 is not legal

2016-10-10 20:45:15 +00:00

NVPTX

[NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions.

2016-09-28 17:25:38 +00:00

PowerPC

[PPCMIPeephole] Fix splat elimination

2016-10-12 00:48:25 +00:00

SPARC

This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included.

2016-10-10 08:53:06 +00:00

SystemZ

[DAGCombiner] Do not remove the load of stored values when optimizations are disabled

2016-10-12 13:44:24 +00:00

Thumb

Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"

2016-10-11 21:14:03 +00:00

Thumb2

Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"

2016-10-11 21:14:03 +00:00

WebAssembly

Codegen: Tail-duplicate during placement.

2016-10-11 20:36:43 +00:00

WinEH

Revert EH-specific checks in BranchFolding that were causing blow ups in compile time.

2016-07-27 17:55:33 +00:00

X86

[x86] add negate-i1 run for 32-bit target

2016-10-13 14:27:08 +00:00

XCore

Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."

2016-09-28 16:37:50 +00:00