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fb7e70c44e
Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware support, but only for conversions between float and double. Also add the necessary boilerplate so that the LegalizerHelper can introduce the required libcalls. This also works only for float and double, but isn't too difficult to extend when the need arises. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322651 91177308-0d34-0410-b5e6-96231b3b80d8
993 lines
35 KiB
C++
993 lines
35 KiB
C++
//===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizerHelper class to legalize
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/// individual instructions and the LegalizeMachineIR wrapper pass for the
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/// primary legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "legalizer"
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using namespace llvm;
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LegalizerHelper::LegalizerHelper(MachineFunction &MF)
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: MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
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MIRBuilder.setMF(MF);
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
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DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
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auto Action = LI.getAction(MI, MRI);
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switch (std::get<0>(Action)) {
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case LegalizerInfo::Legal:
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DEBUG(dbgs() << ".. Already legal\n");
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return AlreadyLegal;
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case LegalizerInfo::Libcall:
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DEBUG(dbgs() << ".. Convert to libcall\n");
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return libcall(MI);
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case LegalizerInfo::NarrowScalar:
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DEBUG(dbgs() << ".. Narrow scalar\n");
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return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::WidenScalar:
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DEBUG(dbgs() << ".. Widen scalar\n");
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return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Lower:
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DEBUG(dbgs() << ".. Lower\n");
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return lower(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::FewerElements:
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DEBUG(dbgs() << ".. Reduce number of elements\n");
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return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Custom:
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DEBUG(dbgs() << ".. Custom legalization\n");
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return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
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: UnableToLegalize;
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default:
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DEBUG(dbgs() << ".. Unable to legalize\n");
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return UnableToLegalize;
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}
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}
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void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &VRegs) {
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for (int i = 0; i < NumParts; ++i)
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VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
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MIRBuilder.buildUnmerge(VRegs, Reg);
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}
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static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
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switch (Opcode) {
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case TargetOpcode::G_SDIV:
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assert(Size == 32 && "Unsupported size");
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return RTLIB::SDIV_I32;
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case TargetOpcode::G_UDIV:
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assert(Size == 32 && "Unsupported size");
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return RTLIB::UDIV_I32;
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case TargetOpcode::G_SREM:
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assert(Size == 32 && "Unsupported size");
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return RTLIB::SREM_I32;
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case TargetOpcode::G_UREM:
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assert(Size == 32 && "Unsupported size");
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return RTLIB::UREM_I32;
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case TargetOpcode::G_FADD:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
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case TargetOpcode::G_FSUB:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
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case TargetOpcode::G_FMUL:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
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case TargetOpcode::G_FDIV:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
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case TargetOpcode::G_FREM:
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return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
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case TargetOpcode::G_FPOW:
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return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
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case TargetOpcode::G_FMA:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
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}
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llvm_unreachable("Unknown libcall function");
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}
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LegalizerHelper::LegalizeResult
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llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
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const CallLowering::ArgInfo &Result,
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ArrayRef<CallLowering::ArgInfo> Args) {
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auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
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auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
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const char *Name = TLI.getLibcallName(Libcall);
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MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
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if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
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MachineOperand::CreateES(Name), Result, Args))
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return LegalizerHelper::UnableToLegalize;
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return LegalizerHelper::Legalized;
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}
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// Useful for libcalls where all operands have the same type.
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static LegalizerHelper::LegalizeResult
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simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
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Type *OpType) {
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auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
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SmallVector<CallLowering::ArgInfo, 3> Args;
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for (unsigned i = 1; i < MI.getNumOperands(); i++)
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Args.push_back({MI.getOperand(i).getReg(), OpType});
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return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
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Args);
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}
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static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
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Type *FromType) {
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auto ToMVT = MVT::getVT(ToType);
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auto FromMVT = MVT::getVT(FromType);
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switch (Opcode) {
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case TargetOpcode::G_FPEXT:
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return RTLIB::getFPEXT(FromMVT, ToMVT);
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case TargetOpcode::G_FPTRUNC:
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return RTLIB::getFPROUND(FromMVT, ToMVT);
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}
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llvm_unreachable("Unsupported libcall function");
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}
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static LegalizerHelper::LegalizeResult
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conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
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Type *FromType) {
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RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
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return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
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{{MI.getOperand(1).getReg(), FromType}});
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::libcall(MachineInstr &MI) {
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LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
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unsigned Size = LLTy.getSizeInBits();
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auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UDIV:
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case TargetOpcode::G_SREM:
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case TargetOpcode::G_UREM: {
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Type *HLTy = Type::getInt32Ty(Ctx);
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auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
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if (Status != Legalized)
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return Status;
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break;
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}
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FMA:
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FREM: {
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Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
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auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
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if (Status != Legalized)
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return Status;
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break;
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}
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case TargetOpcode::G_FPEXT: {
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// FIXME: Support other floating point types (half, fp128 etc)
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unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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if (ToSize != 64 || FromSize != 32)
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return UnableToLegalize;
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LegalizeResult Status = conversionLibcall(
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MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
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if (Status != Legalized)
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return Status;
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break;
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}
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case TargetOpcode::G_FPTRUNC: {
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// FIXME: Support other floating point types (half, fp128 etc)
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unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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if (ToSize != 32 || FromSize != 64)
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return UnableToLegalize;
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LegalizeResult Status = conversionLibcall(
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MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
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if (Status != Legalized)
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return Status;
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break;
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}
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}
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
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return UnableToLegalize;
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MIRBuilder.setInstr(MI);
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int64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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int64_t NarrowSize = NarrowTy.getSizeInBits();
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_IMPLICIT_DEF: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowSize;
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SmallVector<unsigned, 2> DstRegs;
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for (int i = 0; i < NumParts; ++i) {
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unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildUndef(Dst);
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DstRegs.push_back(Dst);
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_ADD: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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// Expand in terms of carry-setting/consuming G_ADDE instructions.
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int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildConstant(CarryIn, 0);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
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Src2Regs[i], CarryIn);
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DstRegs.push_back(DstReg);
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CarryIn = CarryOut;
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_EXTRACT: {
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if (TypeIdx != 1)
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return UnableToLegalize;
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int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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// FIXME: add support for when SizeOp1 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp1 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp1 / NarrowSize;
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SmallVector<unsigned, 2> SrcRegs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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unsigned OpReg = MI.getOperand(0).getReg();
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int64_t OpStart = MI.getOperand(2).getImm();
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int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
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for (int i = 0; i < NumParts; ++i) {
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unsigned SrcStart = i * NarrowSize;
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if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
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// No part of the extract uses this subregister, ignore it.
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continue;
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} else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
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// The entire subregister is extracted, forward the value.
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DstRegs.push_back(SrcRegs[i]);
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continue;
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}
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// OpSegStart is where this destination segment would start in OpReg if it
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// extended infinitely in both directions.
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int64_t ExtractOffset, SegSize;
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if (OpStart < SrcStart) {
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ExtractOffset = 0;
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SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
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} else {
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ExtractOffset = OpStart - SrcStart;
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SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
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}
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unsigned SegReg = SrcRegs[i];
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if (ExtractOffset != 0 || SegSize != NarrowSize) {
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// A genuine extract is needed.
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SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
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MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
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}
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DstRegs.push_back(SegReg);
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_INSERT: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowSize;
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SmallVector<unsigned, 2> SrcRegs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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unsigned OpReg = MI.getOperand(2).getReg();
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int64_t OpStart = MI.getOperand(3).getImm();
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int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstStart = i * NarrowSize;
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if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
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// No part of the insert affects this subregister, forward the original.
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DstRegs.push_back(SrcRegs[i]);
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continue;
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} else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
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// The entire subregister is defined by this insert, forward the new
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// value.
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DstRegs.push_back(OpReg);
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continue;
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}
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// OpSegStart is where this destination segment would start in OpReg if it
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// extended infinitely in both directions.
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int64_t ExtractOffset, InsertOffset, SegSize;
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if (OpStart < DstStart) {
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InsertOffset = 0;
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ExtractOffset = DstStart - OpStart;
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SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
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} else {
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InsertOffset = OpStart - DstStart;
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ExtractOffset = 0;
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SegSize =
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std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
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}
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unsigned SegReg = OpReg;
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if (ExtractOffset != 0 || SegSize != OpSize) {
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// A genuine extract is needed.
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SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
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MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
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}
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
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DstRegs.push_back(DstReg);
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}
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assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowSize;
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LLT OffsetTy = LLT::scalar(
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MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
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SmallVector<unsigned, 2> DstRegs;
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg = 0;
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unsigned Adjustment = i * NarrowSize / 8;
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MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
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Adjustment);
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// TODO: This is conservatively correct, but we probably want to split the
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// memory operands in the future.
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MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
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DstRegs.push_back(DstReg);
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowSize;
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LLT OffsetTy = LLT::scalar(
|
|
MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
|
|
|
|
SmallVector<unsigned, 2> SrcRegs;
|
|
extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
|
|
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = 0;
|
|
unsigned Adjustment = i * NarrowSize / 8;
|
|
|
|
MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
|
|
Adjustment);
|
|
|
|
// TODO: This is conservatively correct, but we probably want to split the
|
|
// memory operands in the future.
|
|
MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
|
|
}
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_CONSTANT: {
|
|
// FIXME: add support for when SizeOp0 isn't an exact multiple of
|
|
// NarrowSize.
|
|
if (SizeOp0 % NarrowSize != 0)
|
|
return UnableToLegalize;
|
|
int NumParts = SizeOp0 / NarrowSize;
|
|
const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
|
|
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
|
|
|
|
SmallVector<unsigned, 2> DstRegs;
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
|
|
ConstantInt *CI =
|
|
ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
|
|
MIRBuilder.buildConstant(DstReg, *CI);
|
|
DstRegs.push_back(DstReg);
|
|
}
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
MIRBuilder.buildMerge(DstReg, DstRegs);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_OR: {
|
|
// Legalize bitwise operation:
|
|
// A = BinOp<Ty> B, C
|
|
// into:
|
|
// B1, ..., BN = G_UNMERGE_VALUES B
|
|
// C1, ..., CN = G_UNMERGE_VALUES C
|
|
// A1 = BinOp<Ty/N> B1, C2
|
|
// ...
|
|
// AN = BinOp<Ty/N> BN, CN
|
|
// A = G_MERGE_VALUES A1, ..., AN
|
|
|
|
// FIXME: add support for when SizeOp0 isn't an exact multiple of
|
|
// NarrowSize.
|
|
if (SizeOp0 % NarrowSize != 0)
|
|
return UnableToLegalize;
|
|
int NumParts = SizeOp0 / NarrowSize;
|
|
|
|
// List the registers where the destination will be scattered.
|
|
SmallVector<unsigned, 2> DstRegs;
|
|
// List the registers where the first argument will be split.
|
|
SmallVector<unsigned, 2> SrcsReg1;
|
|
// List the registers where the second argument will be split.
|
|
SmallVector<unsigned, 2> SrcsReg2;
|
|
// Create all the temporary registers.
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
|
|
unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
|
|
unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
|
|
|
|
DstRegs.push_back(DstReg);
|
|
SrcsReg1.push_back(SrcReg1);
|
|
SrcsReg2.push_back(SrcReg2);
|
|
}
|
|
// Explode the big arguments into smaller chunks.
|
|
MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
|
|
MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
|
|
|
|
// Do the operation on each small part.
|
|
for (int i = 0; i < NumParts; ++i)
|
|
MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]);
|
|
|
|
// Gather the destination registers into the final destination.
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
MIRBuilder.buildMerge(DstReg, DstRegs);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_XOR:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_SHL: {
|
|
// Perform operation at larger width (any extension is fine here, high bits
|
|
// don't affect the result) and then truncate the result back to the
|
|
// original type.
|
|
unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
|
|
MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
|
|
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(MI.getOpcode())
|
|
.addDef(DstExt)
|
|
.addUse(Src1Ext)
|
|
.addUse(Src2Ext);
|
|
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UDIV:
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM:
|
|
case TargetOpcode::G_ASHR:
|
|
case TargetOpcode::G_LSHR: {
|
|
unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
|
|
MI.getOpcode() == TargetOpcode::G_SREM ||
|
|
MI.getOpcode() == TargetOpcode::G_ASHR
|
|
? TargetOpcode::G_SEXT
|
|
: TargetOpcode::G_ZEXT;
|
|
|
|
unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
|
|
MI.getOperand(1).getReg());
|
|
|
|
unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
|
|
MI.getOperand(2).getReg());
|
|
|
|
unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(MI.getOpcode())
|
|
.addDef(ResExt)
|
|
.addUse(LHSExt)
|
|
.addUse(RHSExt);
|
|
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SELECT: {
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
|
|
// Perform operation at larger width (any extension is fine here, high bits
|
|
// don't affect the result) and then truncate the result back to the
|
|
// original type.
|
|
unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
|
|
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
|
|
.addDef(DstExt)
|
|
.addReg(MI.getOperand(1).getReg())
|
|
.addUse(Src1Ext)
|
|
.addUse(Src2Ext);
|
|
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FPTOSI:
|
|
case TargetOpcode::G_FPTOUI: {
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(MI.getOpcode())
|
|
.addDef(DstExt)
|
|
.addUse(MI.getOperand(1).getReg());
|
|
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SITOFP:
|
|
case TargetOpcode::G_UITOFP: {
|
|
if (TypeIdx != 1)
|
|
return UnableToLegalize;
|
|
|
|
unsigned Src = MI.getOperand(1).getReg();
|
|
unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
|
|
|
|
if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
|
|
MIRBuilder.buildSExt(SrcExt, Src);
|
|
} else {
|
|
assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
|
|
MIRBuilder.buildZExt(SrcExt, Src);
|
|
}
|
|
|
|
MIRBuilder.buildInstr(MI.getOpcode())
|
|
.addDef(MI.getOperand(0).getReg())
|
|
.addUse(SrcExt);
|
|
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_INSERT: {
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
|
|
unsigned Src = MI.getOperand(1).getReg();
|
|
unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(SrcExt, Src);
|
|
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
|
|
MI.getOperand(3).getImm());
|
|
for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
|
|
MIB.addReg(MI.getOperand(OpNum).getReg());
|
|
MIB.addImm(MI.getOperand(OpNum + 1).getImm());
|
|
}
|
|
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_LOAD: {
|
|
assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
|
|
WideTy.getSizeInBits() &&
|
|
"illegal to increase number of bytes loaded");
|
|
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
|
|
**MI.memoperands_begin());
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_STORE: {
|
|
if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
|
|
WideTy != LLT::scalar(8))
|
|
return UnableToLegalize;
|
|
|
|
auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
|
|
auto Content = TLI.getBooleanContents(false, false);
|
|
|
|
unsigned ExtOp = TargetOpcode::G_ANYEXT;
|
|
if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
|
|
ExtOp = TargetOpcode::G_ZEXT;
|
|
else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
|
|
ExtOp = TargetOpcode::G_SEXT;
|
|
else
|
|
ExtOp = TargetOpcode::G_ANYEXT;
|
|
|
|
unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
|
|
MI.getOperand(0).getReg());
|
|
MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
|
|
**MI.memoperands_begin());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_CONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FCONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
|
|
MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_BRCOND: {
|
|
unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
|
|
MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FCMP: {
|
|
unsigned Op0Ext, Op1Ext, DstReg;
|
|
unsigned Cmp1 = MI.getOperand(2).getReg();
|
|
unsigned Cmp2 = MI.getOperand(3).getReg();
|
|
if (TypeIdx == 0) {
|
|
Op0Ext = Cmp1;
|
|
Op1Ext = Cmp2;
|
|
DstReg = MRI.createGenericVirtualRegister(WideTy);
|
|
} else {
|
|
Op0Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
Op1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
DstReg = MI.getOperand(0).getReg();
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op0Ext, Cmp1);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op1Ext, Cmp2);
|
|
}
|
|
MIRBuilder.buildFCmp(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
|
|
DstReg, Op0Ext, Op1Ext);
|
|
if (TypeIdx == 0)
|
|
MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
|
|
DstReg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_ICMP: {
|
|
bool IsSigned = CmpInst::isSigned(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
|
|
unsigned Cmp1 = MI.getOperand(2).getReg();
|
|
unsigned Cmp2 = MI.getOperand(3).getReg();
|
|
unsigned Op0Ext, Op1Ext, DstReg;
|
|
if (TypeIdx == 0) {
|
|
Op0Ext = Cmp1;
|
|
Op1Ext = Cmp2;
|
|
DstReg = MRI.createGenericVirtualRegister(WideTy);
|
|
} else {
|
|
Op0Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
Op1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
DstReg = MI.getOperand(0).getReg();
|
|
if (IsSigned) {
|
|
MIRBuilder.buildSExt(Op0Ext, Cmp1);
|
|
MIRBuilder.buildSExt(Op1Ext, Cmp2);
|
|
} else {
|
|
MIRBuilder.buildZExt(Op0Ext, Cmp1);
|
|
MIRBuilder.buildZExt(Op1Ext, Cmp2);
|
|
}
|
|
}
|
|
MIRBuilder.buildICmp(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
|
|
DstReg, Op0Ext, Op1Ext);
|
|
if (TypeIdx == 0)
|
|
MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
|
|
DstReg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_GEP: {
|
|
assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
|
|
unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
|
|
MI.getOperand(2).setReg(OffsetExt);
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_PHI: {
|
|
assert(TypeIdx == 0 && "Expecting only Idx 0");
|
|
auto getExtendedReg = [&](unsigned Reg, MachineBasicBlock &MBB) {
|
|
auto FirstTermIt = MBB.getFirstTerminator();
|
|
MIRBuilder.setInsertPt(MBB, FirstTermIt);
|
|
MachineInstr *DefMI = MRI.getVRegDef(Reg);
|
|
MachineInstrBuilder MIB;
|
|
if (DefMI->getOpcode() == TargetOpcode::G_TRUNC)
|
|
MIB = MIRBuilder.buildAnyExtOrTrunc(WideTy,
|
|
DefMI->getOperand(1).getReg());
|
|
else
|
|
MIB = MIRBuilder.buildAnyExt(WideTy, Reg);
|
|
return MIB->getOperand(0).getReg();
|
|
};
|
|
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, WideTy);
|
|
for (auto OpIt = MI.operands_begin() + 1, OpE = MI.operands_end();
|
|
OpIt != OpE;) {
|
|
unsigned Reg = OpIt++->getReg();
|
|
MachineBasicBlock *OpMBB = OpIt++->getMBB();
|
|
MIB.addReg(getExtendedReg(Reg, *OpMBB));
|
|
MIB.addMBB(OpMBB);
|
|
}
|
|
auto *MBB = MI.getParent();
|
|
MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(),
|
|
MIB->getOperand(0).getReg());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
|
|
using namespace TargetOpcode;
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
switch(MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM: {
|
|
unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
|
|
.addDef(QuotReg)
|
|
.addUse(MI.getOperand(1).getReg())
|
|
.addUse(MI.getOperand(2).getReg());
|
|
|
|
unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
|
|
ProdReg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SMULO:
|
|
case TargetOpcode::G_UMULO: {
|
|
// Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
|
|
// result.
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
unsigned Overflow = MI.getOperand(1).getReg();
|
|
unsigned LHS = MI.getOperand(2).getReg();
|
|
unsigned RHS = MI.getOperand(3).getReg();
|
|
|
|
MIRBuilder.buildMul(Res, LHS, RHS);
|
|
|
|
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
|
|
? TargetOpcode::G_SMULH
|
|
: TargetOpcode::G_UMULH;
|
|
|
|
unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(Opcode)
|
|
.addDef(HiPart)
|
|
.addUse(LHS)
|
|
.addUse(RHS);
|
|
|
|
unsigned Zero = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildConstant(Zero, 0);
|
|
|
|
// For *signed* multiply, overflow is detected by checking:
|
|
// (hi != (lo >> bitwidth-1))
|
|
if (Opcode == TargetOpcode::G_SMULH) {
|
|
unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
|
|
unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
|
|
.addDef(Shifted)
|
|
.addUse(Res)
|
|
.addUse(ShiftAmt);
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
|
|
} else {
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
|
|
}
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FNEG: {
|
|
// TODO: Handle vector types once we are able to
|
|
// represent them.
|
|
if (Ty.isVector())
|
|
return UnableToLegalize;
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
Type *ZeroTy;
|
|
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
|
|
switch (Ty.getSizeInBits()) {
|
|
case 16:
|
|
ZeroTy = Type::getHalfTy(Ctx);
|
|
break;
|
|
case 32:
|
|
ZeroTy = Type::getFloatTy(Ctx);
|
|
break;
|
|
case 64:
|
|
ZeroTy = Type::getDoubleTy(Ctx);
|
|
break;
|
|
case 128:
|
|
ZeroTy = Type::getFP128Ty(Ctx);
|
|
break;
|
|
default:
|
|
llvm_unreachable("unexpected floating-point type");
|
|
}
|
|
ConstantFP &ZeroForNegation =
|
|
*cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
|
|
unsigned Zero = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildFConstant(Zero, ZeroForNegation);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
|
|
.addDef(Res)
|
|
.addUse(Zero)
|
|
.addUse(MI.getOperand(1).getReg());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FSUB: {
|
|
// Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
|
|
// First, check if G_FNEG is marked as Lower. If so, we may
|
|
// end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
|
|
if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
|
|
return UnableToLegalize;
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
unsigned LHS = MI.getOperand(1).getReg();
|
|
unsigned RHS = MI.getOperand(2).getReg();
|
|
unsigned Neg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FADD)
|
|
.addDef(Res)
|
|
.addUse(LHS)
|
|
.addUse(Neg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
|
|
unsigned OldValRes = MI.getOperand(0).getReg();
|
|
unsigned SuccessRes = MI.getOperand(1).getReg();
|
|
unsigned Addr = MI.getOperand(2).getReg();
|
|
unsigned CmpVal = MI.getOperand(3).getReg();
|
|
unsigned NewVal = MI.getOperand(4).getReg();
|
|
MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
|
|
**MI.memoperands_begin());
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
|
|
LLT NarrowTy) {
|
|
// FIXME: Don't know how to handle secondary types yet.
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_ADD: {
|
|
unsigned NarrowSize = NarrowTy.getSizeInBits();
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
unsigned Size = MRI.getType(DstReg).getSizeInBits();
|
|
int NumParts = Size / NarrowSize;
|
|
// FIXME: Don't know how to handle the situation where the small vectors
|
|
// aren't all the same size yet.
|
|
if (Size % NarrowSize != 0)
|
|
return UnableToLegalize;
|
|
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
|
|
extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
|
|
extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
|
|
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
|
|
MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
|
|
DstRegs.push_back(DstReg);
|
|
}
|
|
|
|
MIRBuilder.buildMerge(DstReg, DstRegs);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|