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287d498bc5
https://reviews.llvm.org/D55294 Previously MachineIRBuilder::buildInstr used to accept variadic arguments for sources (which were either unsigned or MachineInstrBuilder). While this worked well in common cases, it doesn't allow us to build instructions that have multiple destinations. Additionally passing in other optional parameters in the end (such as flags) is not possible trivially. Also a trivial call such as B.buildInstr(Opc, Reg1, Reg2, Reg3) can be interpreted differently based on the opcode (2defs + 1 src for unmerge vs 1 def + 2srcs). This patch refactors the buildInstr to buildInstr(Opc, ArrayRef<DstOps>, ArrayRef<SrcOps>) where DstOps and SrcOps are typed unions that know how to add itself to MachineInstrBuilder. After this patch, most invocations would look like B.buildInstr(Opc, {s32, DstReg}, {SrcRegs..., SrcMIBs..}); Now all the other calls (such as buildAdd, buildSub etc) forward to buildInstr. It also makes it possible to build instructions with multiple defs. Additionally in a subsequent patch, we should make it possible to add flags directly while building instructions. Additionally, the main buildInstr method is now virtual and other builders now only have to override buildInstr (for say constant folding/cseing) is straightforward. Also attached here (https://reviews.llvm.org/F7675680) is a clang-tidy patch that should upgrade the API calls if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348815 91177308-0d34-0410-b5e6-96231b3b80d8
1000 lines
39 KiB
C++
1000 lines
39 KiB
C++
//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the MachineIRBuidler class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugInfo.h"
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using namespace llvm;
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void MachineIRBuilder::setMF(MachineFunction &MF) {
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State.MF = &MF;
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State.MBB = nullptr;
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State.MRI = &MF.getRegInfo();
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State.TII = MF.getSubtarget().getInstrInfo();
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State.DL = DebugLoc();
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State.II = MachineBasicBlock::iterator();
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State.Observer = nullptr;
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}
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void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
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State.MBB = &MBB;
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State.II = MBB.end();
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assert(&getMF() == MBB.getParent() &&
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"Basic block is in a different function");
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}
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void MachineIRBuilder::setInstr(MachineInstr &MI) {
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assert(MI.getParent() && "Instruction is not part of a basic block");
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setMBB(*MI.getParent());
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State.II = MI.getIterator();
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}
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void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II) {
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assert(MBB.getParent() == &getMF() &&
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"Basic block is in a different function");
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State.MBB = &MBB;
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State.II = II;
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}
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void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
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if (State.Observer)
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State.Observer->createdInstr(*InsertedInstr);
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}
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void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
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State.Observer = &Observer;
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}
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void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
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//------------------------------------------------------------------------------
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// Build instruction variants.
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//------------------------------------------------------------------------------
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MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
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return insertInstr(buildInstrNoInsert(Opcode));
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}
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MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
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MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
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getMBB().insert(getInsertPt(), MIB);
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recordInsertion(MIB);
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return MIB;
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}
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MachineInstrBuilder
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MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ false, Reg, Variable, Expr));
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}
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MachineInstrBuilder
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MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ true, Reg, Variable, Expr));
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}
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MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
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const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return buildInstr(TargetOpcode::DBG_VALUE)
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.addFrameIndex(FI)
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.addImm(0)
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.addMetadata(Variable)
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.addMetadata(Expr);
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}
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MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
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const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
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if (auto *CI = dyn_cast<ConstantInt>(&C)) {
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if (CI->getBitWidth() > 64)
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MIB.addCImm(CI);
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else
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MIB.addImm(CI->getZExtValue());
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} else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
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MIB.addFPImm(CFP);
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} else {
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// Insert %noreg if we didn't find a usable constant and had to drop it.
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MIB.addReg(0U);
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}
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return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
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}
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MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
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assert(isa<DILabel>(Label) && "not a label");
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assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
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return MIB.addMetadata(Label);
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}
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MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
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assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
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return buildInstr(TargetOpcode::G_FRAME_INDEX)
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.addDef(Res)
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.addFrameIndex(Idx);
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}
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MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
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const GlobalValue *GV) {
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assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
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assert(getMRI()->getType(Res).getAddressSpace() ==
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GV->getType()->getAddressSpace() &&
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"address space mismatch");
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return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
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.addDef(Res)
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.addGlobalAddress(GV);
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}
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void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
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const LLT &Op1) {
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assert(Res.isScalar() || Res.isVector() && "invalid operand type");
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assert((Res == Op0 && Res == Op1) && "type mismatch");
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}
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MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
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unsigned Op1) {
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assert(getMRI()->getType(Res).isPointer() &&
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getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
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assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
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return buildInstr(TargetOpcode::G_GEP)
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.addDef(Res)
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.addUse(Op0)
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.addUse(Op1);
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}
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Optional<MachineInstrBuilder>
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MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
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const LLT &ValueTy, uint64_t Value) {
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assert(Res == 0 && "Res is a result argument");
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assert(ValueTy.isScalar() && "invalid offset type");
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if (Value == 0) {
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Res = Op0;
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return None;
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}
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Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
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unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
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buildConstant(TmpReg, Value);
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return buildGEP(Res, Op0, TmpReg);
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}
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MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
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uint32_t NumBits) {
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assert(getMRI()->getType(Res).isPointer() &&
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getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
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return buildInstr(TargetOpcode::G_PTR_MASK)
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.addDef(Res)
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.addUse(Op0)
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.addImm(NumBits);
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}
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MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
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return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
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}
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MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
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assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
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return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
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}
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MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::COPY, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
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const ConstantInt &Val) {
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LLT Ty = Res.getLLTTy(*getMRI());
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assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
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const ConstantInt *NewVal = &Val;
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if (Ty.getSizeInBits() != Val.getBitWidth())
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NewVal = ConstantInt::get(getMF().getFunction().getContext(),
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Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
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auto MIB = buildInstr(TargetOpcode::G_CONSTANT);
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Res.addDefToMIB(*getMRI(), MIB);
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MIB.addCImm(NewVal);
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
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int64_t Val) {
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auto IntN = IntegerType::get(getMF().getFunction().getContext(),
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Res.getLLTTy(*getMRI()).getSizeInBits());
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ConstantInt *CI = ConstantInt::get(IntN, Val, true);
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return buildConstant(Res, *CI);
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}
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MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
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const ConstantFP &Val) {
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assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
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auto MIB = buildInstr(TargetOpcode::G_FCONSTANT);
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Res.addDefToMIB(*getMRI(), MIB);
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MIB.addFPImm(&Val);
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
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double Val) {
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LLT DstTy = Res.getLLTTy(*getMRI());
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auto &Ctx = getMF().getFunction().getContext();
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auto *CFP =
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ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits()));
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return buildFConstant(Res, *CFP);
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}
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MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
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MachineBasicBlock &Dest) {
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assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
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return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
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}
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MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
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MachineMemOperand &MMO) {
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return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
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unsigned Res,
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unsigned Addr,
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MachineMemOperand &MMO) {
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
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return buildInstr(Opcode)
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.addDef(Res)
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.addUse(Addr)
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.addMemOperand(&MMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
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MachineMemOperand &MMO) {
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assert(getMRI()->getType(Val).isValid() && "invalid operand type");
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assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
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return buildInstr(TargetOpcode::G_STORE)
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.addUse(Val)
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.addUse(Addr)
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.addMemOperand(&MMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
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const DstOp &CarryOut,
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const SrcOp &Op0,
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const SrcOp &Op1,
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const SrcOp &CarryIn) {
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return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
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{Op0, Op1, CarryIn});
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}
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MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_SEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
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const DstOp &Res,
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const SrcOp &Op) {
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assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
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TargetOpcode::G_SEXT == ExtOpc) &&
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"Expecting Extending Opc");
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assert(Res.getLLTTy(*getMRI()).isScalar() ||
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Res.getLLTTy(*getMRI()).isVector());
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assert(Res.getLLTTy(*getMRI()).isScalar() ==
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Op.getLLTTy(*getMRI()).isScalar());
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unsigned Opcode = TargetOpcode::COPY;
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if (Res.getLLTTy(*getMRI()).getSizeInBits() >
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Op.getLLTTy(*getMRI()).getSizeInBits())
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Opcode = ExtOpc;
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else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
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Op.getLLTTy(*getMRI()).getSizeInBits())
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Opcode = TargetOpcode::G_TRUNC;
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else
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assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
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return buildInstr(Opcode, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
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const SrcOp &Op) {
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return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
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const SrcOp &Op) {
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return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
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const SrcOp &Op) {
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return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
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const SrcOp &Src) {
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LLT SrcTy = Src.getLLTTy(*getMRI());
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LLT DstTy = Dst.getLLTTy(*getMRI());
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if (SrcTy == DstTy)
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return buildCopy(Dst, Src);
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unsigned Opcode;
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if (SrcTy.isPointer() && DstTy.isScalar())
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Opcode = TargetOpcode::G_PTRTOINT;
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else if (DstTy.isPointer() && SrcTy.isScalar())
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Opcode = TargetOpcode::G_INTTOPTR;
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else {
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assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
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Opcode = TargetOpcode::G_BITCAST;
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}
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return buildInstr(Opcode, Dst, Src);
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}
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MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
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uint64_t Index) {
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#ifndef NDEBUG
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assert(getMRI()->getType(Src).isValid() && "invalid operand type");
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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assert(Index + getMRI()->getType(Res).getSizeInBits() <=
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getMRI()->getType(Src).getSizeInBits() &&
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"extracting off end of register");
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#endif
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if (getMRI()->getType(Res).getSizeInBits() ==
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getMRI()->getType(Src).getSizeInBits()) {
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assert(Index == 0 && "insertion past the end of a register");
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return buildCast(Res, Src);
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}
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return buildInstr(TargetOpcode::G_EXTRACT)
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.addDef(Res)
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.addUse(Src)
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.addImm(Index);
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}
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void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
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ArrayRef<uint64_t> Indices) {
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#ifndef NDEBUG
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assert(Ops.size() == Indices.size() && "incompatible args");
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assert(!Ops.empty() && "invalid trivial sequence");
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assert(std::is_sorted(Indices.begin(), Indices.end()) &&
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"sequence offsets must be in ascending order");
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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for (auto Op : Ops)
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assert(getMRI()->getType(Op).isValid() && "invalid operand type");
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#endif
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LLT ResTy = getMRI()->getType(Res);
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LLT OpTy = getMRI()->getType(Ops[0]);
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unsigned OpSize = OpTy.getSizeInBits();
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bool MaybeMerge = true;
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for (unsigned i = 0; i < Ops.size(); ++i) {
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if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
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MaybeMerge = false;
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break;
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}
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}
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if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
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buildMerge(Res, Ops);
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return;
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}
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unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
|
|
buildUndef(ResIn);
|
|
|
|
for (unsigned i = 0; i < Ops.size(); ++i) {
|
|
unsigned ResOut = i + 1 == Ops.size()
|
|
? Res
|
|
: getMRI()->createGenericVirtualRegister(ResTy);
|
|
buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
|
|
ResIn = ResOut;
|
|
}
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
|
|
return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
|
|
ArrayRef<unsigned> Ops) {
|
|
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
|
|
const SrcOp &Op) {
|
|
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
|
|
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
|
|
const SrcOp &Op) {
|
|
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
|
|
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
|
|
ArrayRef<unsigned> Ops) {
|
|
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
|
|
ArrayRef<unsigned> Ops) {
|
|
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
|
|
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
|
|
unsigned Op, unsigned Index) {
|
|
assert(Index + getMRI()->getType(Op).getSizeInBits() <=
|
|
getMRI()->getType(Res).getSizeInBits() &&
|
|
"insertion past the end of a register");
|
|
|
|
if (getMRI()->getType(Res).getSizeInBits() ==
|
|
getMRI()->getType(Op).getSizeInBits()) {
|
|
return buildCast(Res, Op);
|
|
}
|
|
|
|
return buildInstr(TargetOpcode::G_INSERT)
|
|
.addDef(Res)
|
|
.addUse(Src)
|
|
.addUse(Op)
|
|
.addImm(Index);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
|
|
unsigned Res,
|
|
bool HasSideEffects) {
|
|
auto MIB =
|
|
buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
|
|
: TargetOpcode::G_INTRINSIC);
|
|
if (Res)
|
|
MIB.addDef(Res);
|
|
MIB.addIntrinsicID(ID);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
|
|
const SrcOp &Op) {
|
|
return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
|
|
const SrcOp &Op) {
|
|
return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
|
|
const DstOp &Res,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1) {
|
|
return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
|
|
const DstOp &Res,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1) {
|
|
|
|
return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
|
|
const SrcOp &Tst,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1) {
|
|
|
|
return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
|
|
const SrcOp &Elt, const SrcOp &Idx) {
|
|
return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
|
|
const SrcOp &Idx) {
|
|
return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
|
|
unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
|
|
unsigned NewVal, MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT SuccessResTy = getMRI()->getType(SuccessRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(SuccessResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
|
|
.addDef(OldValRes)
|
|
.addDef(SuccessRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
|
|
unsigned CmpVal, unsigned NewVal,
|
|
MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
|
|
.addDef(OldValRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
|
|
unsigned OldValRes,
|
|
unsigned Addr,
|
|
unsigned Val,
|
|
MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT ValTy = getMRI()->getType(Val);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(ValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == ValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(Opcode)
|
|
.addDef(OldValRes)
|
|
.addUse(Addr)
|
|
.addUse(Val)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
|
|
unsigned Addr,
|
|
unsigned Val,
|
|
MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
|
|
#ifndef NDEBUG
|
|
assert(getMRI()->getType(Res).isPointer() && "invalid res type");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
|
|
}
|
|
|
|
void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
|
|
bool IsExtend) {
|
|
#ifndef NDEBUG
|
|
if (DstTy.isVector()) {
|
|
assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
|
|
assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
|
|
"different number of elements in a trunc/ext");
|
|
} else
|
|
assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
|
|
|
|
if (IsExtend)
|
|
assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
|
|
"invalid narrowing extend");
|
|
else
|
|
assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
|
|
"invalid widening trunc");
|
|
#endif
|
|
}
|
|
|
|
void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
|
|
const LLT &Op0Ty, const LLT &Op1Ty) {
|
|
#ifndef NDEBUG
|
|
assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
|
|
"invalid operand type");
|
|
assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
|
|
if (ResTy.isScalar() || ResTy.isPointer())
|
|
assert(TstTy.isScalar() && "type mismatch");
|
|
else
|
|
assert((TstTy.isScalar() ||
|
|
(TstTy.isVector() &&
|
|
TstTy.getNumElements() == Op0Ty.getNumElements())) &&
|
|
"type mismatch");
|
|
#endif
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
|
|
ArrayRef<DstOp> DstOps,
|
|
ArrayRef<SrcOp> SrcOps) {
|
|
switch (Opc) {
|
|
default:
|
|
break;
|
|
case TargetOpcode::G_SELECT: {
|
|
assert(DstOps.size() == 1 && "Invalid select");
|
|
assert(SrcOps.size() == 3 && "Invalid select");
|
|
validateSelectOp(
|
|
DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
|
|
break;
|
|
}
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_ASHR:
|
|
case TargetOpcode::G_LSHR:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_SHL:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_XOR:
|
|
case TargetOpcode::G_UDIV:
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UREM:
|
|
case TargetOpcode::G_SREM: {
|
|
// All these are binary ops.
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 2 && "Invalid Srcs");
|
|
validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[1].getLLTTy(*getMRI()));
|
|
break;
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_ANYEXT:
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()), true);
|
|
break;
|
|
case TargetOpcode::G_TRUNC:
|
|
case TargetOpcode::G_FPTRUNC:
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()), false);
|
|
break;
|
|
}
|
|
case TargetOpcode::COPY:
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
|
|
SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
|
|
DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
|
|
break;
|
|
case TargetOpcode::G_FCMP:
|
|
case TargetOpcode::G_ICMP: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst Operands");
|
|
assert(SrcOps.size() == 3 && "Invalid Src Operands");
|
|
// For F/ICMP, the first src operand is the predicate, followed by
|
|
// the two comparands.
|
|
assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
|
|
"Expecting predicate");
|
|
assert([&]() -> bool {
|
|
CmpInst::Predicate Pred = SrcOps[0].getPredicate();
|
|
return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
|
|
: CmpInst::isFPPredicate(Pred);
|
|
}() && "Invalid predicate");
|
|
assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
assert([&]() -> bool {
|
|
LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
|
|
LLT DstTy = DstOps[0].getLLTTy(*getMRI());
|
|
if (Op0Ty.isScalar() || Op0Ty.isPointer())
|
|
return DstTy.isScalar();
|
|
else
|
|
return DstTy.isVector() &&
|
|
DstTy.getNumElements() == Op0Ty.getNumElements();
|
|
}() && "Type Mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_UNMERGE_VALUES: {
|
|
assert(!DstOps.empty() && "Invalid trivial sequence");
|
|
assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
|
|
assert(std::all_of(DstOps.begin(), DstOps.end(),
|
|
[&, this](const DstOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
DstOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in output list");
|
|
assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_MERGE_VALUES: {
|
|
assert(!SrcOps.empty() && "invalid trivial sequence");
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
if (SrcOps.size() == 1)
|
|
return buildCast(DstOps[0], SrcOps[0]);
|
|
if (DstOps[0].getLLTTy(*getMRI()).isVector())
|
|
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst size");
|
|
assert(SrcOps.size() == 2 && "Invalid Src size");
|
|
assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
|
|
assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
|
|
DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
|
|
"Invalid operand type");
|
|
assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
|
|
assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
|
|
DstOps[0].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_INSERT_VECTOR_ELT: {
|
|
assert(DstOps.size() == 1 && "Invalid dst size");
|
|
assert(SrcOps.size() == 3 && "Invalid src size");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
|
|
SrcOps[1].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
|
|
SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
|
|
"Type mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BUILD_VECTOR: {
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
"Res type must be a vector");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input scalars do not exactly cover the outpur vector register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
"Res type must be a vector");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_CONCAT_VECTORS: {
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return (Op.getLLTTy(*getMRI()).isVector() &&
|
|
Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI()));
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input vectors do not exactly cover the outpur vector register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_UADDE: {
|
|
assert(DstOps.size() == 2 && "Invalid no of dst operands");
|
|
assert(SrcOps.size() == 3 && "Invalid no of src operands");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
|
|
assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
|
|
(DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
|
|
"Invalid operand");
|
|
assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
|
|
assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
|
|
"type mismatch");
|
|
break;
|
|
}
|
|
}
|
|
|
|
auto MIB = buildInstr(Opc);
|
|
for (const DstOp &Op : DstOps)
|
|
Op.addDefToMIB(*getMRI(), MIB);
|
|
for (const SrcOp &Op : SrcOps)
|
|
Op.addSrcToMIB(MIB);
|
|
return MIB;
|
|
}
|