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74ccbceac1
Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320614 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
5.2 KiB
C++
153 lines
5.2 KiB
C++
//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
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#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
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#include <algorithm>
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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//===----------------------------------------------------------------------===//
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// AMDGPUDisassembler
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//===----------------------------------------------------------------------===//
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint32_t Literal;
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mutable bool HasLiteral;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII) :
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MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()) {}
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~AMDGPUDisassembler() override = default;
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
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DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
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uint64_t Address) const;
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DecodeStatus convertSDWAInst(MCInst &MI) const;
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DecodeStatus convertMIMGInst(MCInst &MI) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VS_128(unsigned Val) const;
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MCOperand decodeOperand_VSrc16(unsigned Val) const;
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MCOperand decodeOperand_VSrcV216(unsigned Val) const;
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MCOperand decodeOperand_VReg_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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MCOperand decodeOperand_SReg_512(unsigned Val) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW128,
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OPW16,
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OPWV216,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
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MCOperand decodeLiteralConstant() const;
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MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSDWASrc16(unsigned Val) const;
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MCOperand decodeSDWASrc32(unsigned Val) const;
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MCOperand decodeSDWAVopcDst(unsigned Val) const;
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int getTTmpIdx(unsigned Val) const;
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bool isVI() const;
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bool isGFX9() const;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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class AMDGPUSymbolizer : public MCSymbolizer {
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private:
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void *DisInfo;
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public:
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AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
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void *disInfo)
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: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
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bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
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int64_t Value, uint64_t Address,
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bool IsBranch, uint64_t Offset,
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uint64_t InstSize) override;
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void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
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int64_t Value,
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uint64_t Address) override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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