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8f5a591f29
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317971 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.3 KiB
C++
129 lines
4.3 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the InstructionSelector class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
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: Renderers(MaxRenderers), MIs() {}
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InstructionSelector::InstructionSelector() = default;
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bool InstructionSelector::constrainOperandRegToRegClass(
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MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
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const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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return
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constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
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}
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bool InstructionSelector::constrainSelectedInstRegOperands(
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MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
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MachineOperand &MO = I.getOperand(OpI);
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// There's nothing to be done on non-register operands.
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if (!MO.isReg())
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continue;
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DEBUG(dbgs() << "Converting operand: " << MO << '\n');
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assert(MO.isReg() && "Unsupported non-reg operand");
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unsigned Reg = MO.getReg();
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// Physical registers don't need to be constrained.
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if (TRI.isPhysicalRegister(Reg))
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continue;
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// Register operands with a value of 0 (e.g. predicate operands) don't need
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// to be constrained.
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if (Reg == 0)
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continue;
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// If the operand is a vreg, we should constrain its regclass, and only
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// insert COPYs if that's impossible.
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// constrainOperandRegClass does that for us.
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MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
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Reg, OpI));
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// Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
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// done.
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if (MO.isUse()) {
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int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
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if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
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I.tieOperands(DefIdx, OpI);
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}
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}
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return true;
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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if (MO.isReg() && MO.getReg())
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if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
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return *VRegVal == Value;
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return false;
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}
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bool InstructionSelector::isBaseWithConstantOffset(
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const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
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if (!Root.isReg())
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return false;
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MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
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if (RootI->getOpcode() != TargetOpcode::G_GEP)
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return false;
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MachineOperand &RHS = RootI->getOperand(2);
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MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
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if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
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return true;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
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MachineInstr &IntoMI) const {
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// Immediate neighbours are already folded.
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if (MI.getParent() == IntoMI.getParent() &&
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std::next(MI.getIterator()) == IntoMI.getIterator())
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return true;
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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}
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