mirror of
https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
7a0dadb15b
If we're going to canonicalize IR towards select of constants, try harder to create those.
Also, don't lose the metadata.
This is actually 4 related transforms in one patch:
// select X, (sext X), C --> select X, -1, C
// select X, (zext X), C --> select X, 1, C
// select X, C, (sext X) --> select X, C, 0
// select X, C, (zext X) --> select X, C, 0
Differential Revision: https://reviews.llvm.org/D25126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283575 91177308-0d34-0410-b5e6-96231b3b80d8
306 lines
9.9 KiB
LLVM
306 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @test_sext1(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_sext1(
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; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = sext i1 %cca to i32
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%r = select i1 %ccb, i32 %ccax, i32 0
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ret i32 %r
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}
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define i32 @test_sext2(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_sext2(
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; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = sext i1 %cca to i32
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%r = select i1 %ccb, i32 -1, i32 %ccax
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ret i32 %r
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}
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define i32 @test_sext3(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_sext3(
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; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true
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; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 [[NOT_CCB]], %cca
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; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = sext i1 %cca to i32
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%r = select i1 %ccb, i32 0, i32 %ccax
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ret i32 %r
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}
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define i32 @test_sext4(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_sext4(
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; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true
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; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 [[NOT_CCB]], %cca
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; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = sext i1 %cca to i32
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%r = select i1 %ccb, i32 %ccax, i32 -1
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ret i32 %r
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}
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define i32 @test_zext1(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_zext1(
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; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = zext i1 %cca to i32
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%r = select i1 %ccb, i32 %ccax, i32 0
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ret i32 %r
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}
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define i32 @test_zext2(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_zext2(
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; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = zext i1 %cca to i32
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%r = select i1 %ccb, i32 1, i32 %ccax
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ret i32 %r
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}
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define i32 @test_zext3(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_zext3(
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; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true
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; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 [[NOT_CCB]], %cca
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = zext i1 %cca to i32
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%r = select i1 %ccb, i32 0, i32 %ccax
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ret i32 %r
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}
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define i32 @test_zext4(i1 %cca, i1 %ccb) {
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; CHECK-LABEL: @test_zext4(
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; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true
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; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 [[NOT_CCB]], %cca
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%ccax = zext i1 %cca to i32
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%r = select i1 %ccb, i32 %ccax, i32 1
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ret i32 %r
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}
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define i32 @test_negative_sext(i1 %a, i1 %cc) {
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; CHECK-LABEL: @test_negative_sext(
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; CHECK-NEXT: [[A_EXT:%.*]] = sext i1 %a to i32
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; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 1
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a.ext = sext i1 %a to i32
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%r = select i1 %cc, i32 %a.ext, i32 1
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ret i32 %r
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}
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define i32 @test_negative_zext(i1 %a, i1 %cc) {
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; CHECK-LABEL: @test_negative_zext(
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; CHECK-NEXT: [[A_EXT:%.*]] = zext i1 %a to i32
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; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 -1
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a.ext = zext i1 %a to i32
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%r = select i1 %cc, i32 %a.ext, i32 -1
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ret i32 %r
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}
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define i32 @test_bits_sext(i8 %a, i1 %cc) {
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; CHECK-LABEL: @test_bits_sext(
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; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 %a to i32
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; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 -128
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a.ext = sext i8 %a to i32
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%r = select i1 %cc, i32 %a.ext, i32 -128
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ret i32 %r
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}
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define i32 @test_bits_zext(i8 %a, i1 %cc) {
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; CHECK-LABEL: @test_bits_zext(
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; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 %a to i32
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; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 255
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a.ext = zext i8 %a to i32
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%r = select i1 %cc, i32 %a.ext, i32 255
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ret i32 %r
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}
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define i32 @test_op_op(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: @test_op_op(
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; CHECK-NEXT: [[CCA:%.*]] = icmp sgt i32 %a, 0
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; CHECK-NEXT: [[CCB:%.*]] = icmp sgt i32 %b, 0
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; CHECK-NEXT: [[CCC:%.*]] = icmp sgt i32 %c, 0
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; CHECK-NEXT: [[R_V:%.*]] = select i1 [[CCC]], i1 [[CCA]], i1 [[CCB]]
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; CHECK-NEXT: [[R:%.*]] = sext i1 [[R:%.*]].v to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cca = icmp sgt i32 %a, 0
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%ccax = sext i1 %cca to i32
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%ccb = icmp sgt i32 %b, 0
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%ccbx = sext i1 %ccb to i32
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%ccc = icmp sgt i32 %c, 0
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%r = select i1 %ccc, i32 %ccax, i32 %ccbx
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ret i32 %r
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}
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define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) {
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; CHECK-LABEL: @test_vectors_sext(
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; CHECK-NEXT: [[FOLD_R:%.*]] = and <2 x i1> %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[FOLD_R]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = sext <2 x i1> %cca to <2 x i32>
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%r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
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ret <2 x i32> %r
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}
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define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
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; CHECK-LABEL: @test_vectors_sext_nonsplat(
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; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> %ccb, <2 x i1> %cca, <2 x i1> <i1 false, i1 true>
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; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = sext <2 x i1> %cca to <2 x i32>
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%r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1>
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ret <2 x i32> %r
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}
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define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) {
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; CHECK-LABEL: @test_vectors_zext(
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; CHECK-NEXT: [[FOLD_R:%.*]] = and <2 x i1> %ccb, %cca
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[FOLD_R]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = zext <2 x i1> %cca to <2 x i32>
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%r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
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ret <2 x i32> %r
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}
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define <2 x i32> @test_vectors_zext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
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; CHECK-LABEL: @test_vectors_zext_nonsplat(
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; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> %ccb, <2 x i1> %cca, <2 x i1> <i1 true, i1 false>
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = zext <2 x i1> %cca to <2 x i32>
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%r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %r
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}
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define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
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; CHECK-LABEL: @scalar_select_of_vectors_sext(
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; CHECK-NEXT: [[FOLD_R:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer
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; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[FOLD_R]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = sext <2 x i1> %cca to <2 x i32>
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%r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
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ret <2 x i32> %r
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}
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define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) {
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; CHECK-LABEL: @scalar_select_of_vectors_zext(
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; CHECK-NEXT: [[FOLD_R:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[FOLD_R]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%ccax = zext <2 x i1> %cca to <2 x i32>
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%r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
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ret <2 x i32> %r
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}
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define i32 @sext_true_val_must_be_all_ones(i1 %x) {
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; CHECK-LABEL: @sext_true_val_must_be_all_ones(
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 -1, i32 42, !prof !0
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; CHECK-NEXT: ret i32 [[SEL]]
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;
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%ext = sext i1 %x to i32
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%sel = select i1 %x, i32 %ext, i32 42, !prof !0
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ret i32 %sel
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}
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define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) {
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; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec(
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 42, i32 12>, !prof !0
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; CHECK-NEXT: ret <2 x i32> [[SEL]]
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;
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%ext = sext <2 x i1> %x to <2 x i32>
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%sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
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ret <2 x i32> %sel
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}
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define i32 @zext_true_val_must_be_one(i1 %x) {
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; CHECK-LABEL: @zext_true_val_must_be_one(
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 1, i32 42, !prof !0
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; CHECK-NEXT: ret i32 [[SEL]]
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;
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%ext = zext i1 %x to i32
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%sel = select i1 %x, i32 %ext, i32 42, !prof !0
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ret i32 %sel
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}
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define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) {
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; CHECK-LABEL: @zext_true_val_must_be_one_vec(
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 42, i32 12>, !prof !0
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; CHECK-NEXT: ret <2 x i32> [[SEL]]
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;
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%ext = zext <2 x i1> %x to <2 x i32>
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%sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
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ret <2 x i32> %sel
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}
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define i32 @sext_false_val_must_be_zero(i1 %x) {
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; CHECK-LABEL: @sext_false_val_must_be_zero(
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 0, !prof !0
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; CHECK-NEXT: ret i32 [[SEL]]
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;
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%ext = sext i1 %x to i32
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%sel = select i1 %x, i32 42, i32 %ext, !prof !0
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ret i32 %sel
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}
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define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) {
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; CHECK-LABEL: @sext_false_val_must_be_zero_vec(
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
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; CHECK-NEXT: ret <2 x i32> [[SEL]]
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;
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%ext = sext <2 x i1> %x to <2 x i32>
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%sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
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ret <2 x i32> %sel
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}
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define i32 @zext_false_val_must_be_zero(i1 %x) {
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; CHECK-LABEL: @zext_false_val_must_be_zero(
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 0, !prof !0
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; CHECK-NEXT: ret i32 [[SEL]]
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;
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%ext = zext i1 %x to i32
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%sel = select i1 %x, i32 42, i32 %ext, !prof !0
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ret i32 %sel
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}
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define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) {
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; CHECK-LABEL: @zext_false_val_must_be_zero_vec(
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
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; CHECK-NEXT: ret <2 x i32> [[SEL]]
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;
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%ext = zext <2 x i1> %x to <2 x i32>
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%sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
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ret <2 x i32> %sel
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}
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!0 = !{!"branch_weights", i32 3, i32 5}
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