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archived-llvm/test/CodeGen/AMDGPU
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Tom Stellard 50dd59a89a Merging r244728: 
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r244728 | Matthew.Arsenault | 2015-08-12 05:04:44 -0400 (Wed, 12 Aug 2015) | 2 lines

AMDGPU: Fix assert on dbg_value instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@253234 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 17:23:30 +00:00
..
32-bit-local-address-space.ll
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add_i64.ll
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add-debug.ll
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add.ll
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address-space.ll
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and.ll
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anyext.ll
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array-ptr-calc-i32.ll
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2015-06-13 03:28:10 +00:00
array-ptr-calc-i64.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
atomic_cmp_swap_local.ll
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2015-06-13 03:28:10 +00:00
atomic_load_add.ll
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atomic_load_sub.ll
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basic-branch.ll
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basic-loop.ll
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bfe_uint.ll
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bfi_int.ll
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big_alu.ll
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bitcast.ll
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bswap.ll
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build_vector.ll
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call_fs.ll
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call.ll
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cayman-loop-bug.ll
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cf_end.ll
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cf-stack-bug.ll
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2015-06-13 03:28:10 +00:00
cgp-addressing-modes.ll
Merging r242673:
2015-07-20 16:46:01 +00:00
coalescer_remat.ll
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2015-06-13 03:28:10 +00:00
codegen-prepare-addrmode-sext.ll
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combine_vloads.ll
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commute_modifiers.ll
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commute-compares.ll
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2015-06-13 03:28:10 +00:00
commute-shifts.ll
AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
2015-06-26 20:29:10 +00:00
complex-folding.ll
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2015-06-13 03:28:10 +00:00
concat_vectors.ll
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copy-illegal-type.ll
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copy-to-reg.ll
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ctlz_zero_undef.ll
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ctpop64.ll
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ctpop.ll
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cttz_zero_undef.ll
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cvt_f32_ubyte.ll
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cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
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2015-06-13 03:28:10 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
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debug.ll
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default-fp-mode.ll
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disconnected-predset-break-bug.ll
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2015-06-13 03:28:10 +00:00
dot4-folding.ll
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2015-06-13 03:28:10 +00:00
ds_read2_offset_order.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2_superreg.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2st64.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_write2.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_write2st64.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds-negative-offset-addressing-mode-loop.ll
AMDGPU/SI: Add debugging subtarget feature for DS offsets
2015-07-06 16:01:58 +00:00
elf.ll
AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
2015-06-26 21:15:11 +00:00
elf.r600.ll
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empty-function.ll
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endcf-loop-header.ll
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extload-private.ll
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extload.ll
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extract_vector_elt_i16.ll
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fabs.f64.ll
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fabs.ll
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fadd64.ll
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fadd.ll
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fceil64.ll
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fceil.ll
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fcmp64.ll
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fcmp-cnd.ll
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fcmp-cnde-int-args.ll
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fcmp.ll
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fconst64.ll
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fcopysign.f32.ll
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fcopysign.f64.ll
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fdiv.f64.ll
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fdiv.ll
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fetch-limits.r600.ll
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fetch-limits.r700+.ll
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ffloor.f64.ll
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ffloor.ll
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flat-address-space.ll
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floor.ll
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fma-combine.ll
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fma.f64.ll
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fma.ll
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fmad.ll
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fmax3.f64.ll
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fmax3.ll
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fmax_legacy.f64.ll
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fmax_legacy.ll
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fmax.ll
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fmaxnum.f64.ll
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fmaxnum.ll
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fmin3.ll
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fmin_legacy.f64.ll
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fmin_legacy.ll
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fmin.ll
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fminnum.f64.ll
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fminnum.ll
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fmul64.ll
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fmul.ll
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fmuladd.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
fnearbyint.ll
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fneg-fabs.f64.ll
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fneg-fabs.ll
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fneg.f64.ll
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fneg.ll
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fp16_to_fp.ll
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fp32_to_fp16.ll
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fp_to_sint.f64.ll
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fp_to_sint.ll
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fp_to_uint.f64.ll
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fp_to_uint.ll
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fp-classify.ll
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fpext.ll
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fptrunc.ll
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frem.ll
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fsqrt.ll
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fsub64.ll
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fsub.ll
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ftrunc.f64.ll
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ftrunc.ll
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gep-address-space.ll
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global_atomics.ll
Merging r242673:
2015-07-20 16:46:01 +00:00
global-directive.ll
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global-extload-i1.ll
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global-extload-i8.ll
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global-extload-i16.ll
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global-extload-i32.ll
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global-zero-initializer.ll
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gv-const-addrspace-fail.ll
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gv-const-addrspace.ll
Merging r243294:
2015-07-27 20:19:04 +00:00
half.ll
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hsa.ll
AMDPGU/SI: Use correct resource descriptors for VI on HSA
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i1-copy-implicit-def.ll
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i1-copy-phi.ll
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i8-to-double-to-float.ll
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icmp64.ll
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icmp-select-sete-reverse-args.ll
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imm.ll
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indirect-addressing-si.ll
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indirect-private-64.ll
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infinite-loop-evergreen.ll
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infinite-loop.ll
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inline-asm.ll
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inline-calls.ll
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input-mods.ll
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insert_subreg.ll
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insert_vector_elt.ll
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invariant-load-no-alias-store.ll
DAGCombiner: Assume invariant load cannot alias a store
2015-07-10 22:17:40 +00:00
jump-address.ll
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kcache-fold.ll
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kernel-args.ll
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large-alloca.ll
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large-constant-initializer.ll
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lds-initializer.ll
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lds-oqap-crash.ll
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lds-output-queue.ll
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lds-size.ll
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lds-zero-initializer.ll
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legalizedag-bug-expand-setcc.ll
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lit.local.cfg
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literals.ll
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llvm.AMDGPU.abs.ll
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llvm.AMDGPU.barrier.global.ll
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llvm.AMDGPU.barrier.local.ll
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llvm.AMDGPU.bfe.i32.ll
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llvm.AMDGPU.bfe.u32.ll
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llvm.AMDGPU.bfi.ll
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llvm.AMDGPU.bfm.ll
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llvm.AMDGPU.brev.ll
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llvm.AMDGPU.clamp.ll
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llvm.AMDGPU.class.ll
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llvm.AMDGPU.cube.ll
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llvm.AMDGPU.cvt_f32_ubyte.ll
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2015-06-13 03:28:10 +00:00
llvm.AMDGPU.div_fixup.ll
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2015-06-13 03:28:10 +00:00
llvm.AMDGPU.div_fmas.ll
AMDGPU/SI: Fix extra space when printing v_div_fmas_*
2015-06-28 18:16:14 +00:00
llvm.AMDGPU.div_scale.ll
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2015-06-13 03:28:10 +00:00
llvm.amdgpu.dp4.ll
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llvm.AMDGPU.flbit.i32.ll
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2015-06-13 03:28:10 +00:00
llvm.AMDGPU.fract.f64.ll
Merging r243263:
2015-07-27 20:17:19 +00:00
llvm.AMDGPU.fract.ll
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2015-06-13 03:28:10 +00:00
llvm.AMDGPU.imad24.ll
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llvm.AMDGPU.imax.ll
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llvm.AMDGPU.imin.ll
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llvm.AMDGPU.imul24.ll
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llvm.AMDGPU.kill.ll
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llvm.amdgpu.kilp.ll
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llvm.AMDGPU.ldexp.ll
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llvm.AMDGPU.legacy.rsq.ll
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llvm.amdgpu.lrp.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
llvm.AMDGPU.mul.ll
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llvm.AMDGPU.rcp.f64.ll
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llvm.AMDGPU.rcp.ll
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llvm.AMDGPU.rsq.clamped.f64.ll
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llvm.AMDGPU.rsq.clamped.ll
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llvm.AMDGPU.rsq.ll
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llvm.AMDGPU.tex.ll
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llvm.AMDGPU.trig_preop.ll
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llvm.AMDGPU.trunc.ll
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llvm.AMDGPU.umad24.ll
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llvm.AMDGPU.umax.ll
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llvm.AMDGPU.umin.ll
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llvm.AMDGPU.umul24.ll
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llvm.cos.ll
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llvm.dbg.value.ll
Merging r244728:
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llvm.exp2.ll
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llvm.log2.ll
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llvm.memcpy.ll
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llvm.pow.ll
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llvm.rint.f64.ll
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llvm.rint.ll
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llvm.round.f64.ll
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llvm.round.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
llvm.SI.fs.interp.ll
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llvm.SI.gather4.ll
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llvm.SI.getlod.ll
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llvm.SI.image.ll
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llvm.SI.image.sample.ll
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llvm.SI.image.sample.o.ll
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llvm.SI.imageload.ll
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llvm.SI.load.dword.ll
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llvm.SI.resinfo.ll
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llvm.SI.sample-masked.ll
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llvm.SI.sample.ll
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llvm.SI.sampled.ll
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llvm.SI.sendmsg-m0.ll
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llvm.SI.sendmsg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.SI.tbuffer.store.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.SI.tid.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.sin.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.sqrt.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load-input-fold.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load.vec.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-atomics64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-atomics.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-memory-two-objects.ll
Fix "the the" in comments.
2015-06-19 01:53:21 +00:00
local-memory.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
loop-address.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
loop-idiom.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lshl.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lshr.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
m0-spill.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mad_int24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mad_uint24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mad-combine.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
mad-sub.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
madak.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
madmk.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
max3.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
max-literals.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
max.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
merge-stores.ll
Revert "Revert "Fix merges of non-zero vector stores""
2015-06-16 15:51:48 +00:00
min3.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
min.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
missing-store.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mubuf.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mul_int24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mul_uint24.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
mul.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mulhu.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
no-initializer-constant-addrspace.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
no-shrink-extloads.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
operand-folding.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
operand-spacing.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
or.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
packetizer.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
parallelandifcollapse.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
parallelorifcollapse.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
predicate-dp4.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
predicates.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
private-memory-atomics.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
private-memory-broken.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
private-memory.ll
Merging r242434:
2015-07-20 16:43:33 +00:00
promote-alloca-bitcast-function.ll
Merging r243461:
2015-11-16 17:23:17 +00:00
promote-alloca-stored-pointer-value.ll
Merging r243462:
2015-11-16 17:23:20 +00:00
pv-packing.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
pv.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
r600-encoding.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
r600-export-fix.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
r600cfg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
README
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
reciprocal.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
register-count-comments.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
reorder-stores.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotl.i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotl.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotr.i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotr.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rsq.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rv7x0_count3.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
s_movk_i32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
saddo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
salu-to-valu.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
scalar_to_vector.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-fs-loop-nested-if.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-fs-loop-nested.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-fs-loop.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-global-loads.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-if-2.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-if.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-kernel-arg-loads.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-vs-if-nested-loop-failure.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-vs-if-nested-loop.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
scratch-buffer.ll
Merging r242434:
2015-07-20 16:43:33 +00:00
sdiv.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sdivrem24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sdivrem64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
select64.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
select-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
select-vectors.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
select.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-cnd.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-cnde-int.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-icmp-select-float.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-opt.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
set-dx10.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setcc64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setcc-equivalent.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setcc-opt.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setcc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
seto.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setuo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sext-eliminate.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sext-in-reg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sgpr-control-flow.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sgpr-copy-duplicate-operand.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sgpr-copy.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
shared-op-cycle.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
shl_add_constant.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
shl_add_ptr.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
shl.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
si-annotate-cf-assertion.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-annotate-cf.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-lod-bias.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-sgpr-spill.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-spill-cf.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-triv-disjoint-mem-access.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-vector-hang.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sign_extend.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
simplify-demanded-bits-build-pair.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sint_to_fp.f64.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
sint_to_fp.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
smrd.ll
Merging r243294:
2015-07-27 20:19:04 +00:00
split-scalar-i64-add.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sra.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
srem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
srl.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
ssubo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-barrier.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-v3i32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-v3i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-vector-ptrs.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store.r600.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
structurize1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
structurize.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sub.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
subreg-coalescer-crash.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
subreg-coalescer-undef-use.ll
Test for specific output in lit test
2015-07-01 22:34:59 +00:00
subreg-eliminate-dead.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
swizzle-export.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
tex-clause-antidep.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
texture-input-merge.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-cmp-constant.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-store-f64-to-f16.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-store-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-store.ll
Merging r243731:
2015-11-16 17:23:25 +00:00
trunc-vector-store-assertion-failure.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
tti-unroll-prefs.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
uaddo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udiv.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udivrem24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udivrem64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udivrem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
uint_to_fp.f64.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
uint_to_fp.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unaligned-load-store.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unhandled-loop-condition-assertion.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unroll.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unsupported-cc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
urecip.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
urem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
use-sgpr-multiple-times.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
usubo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
v1i64-kernel-arg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
v_cndmask.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
v_mac.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
valu-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vector-alloca.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vertex-fetch-encoding.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vop-shrink.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vselect64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vselect.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
vtx-fetch-branch.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vtx-schedule.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
wait.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
work-item-intrinsics.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
wrong-transalu-pos-fix.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
xor.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
zero_extend.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.