Matt Arsenault 4e77263fcb AMDGPU/GlobalISel: Make some G_EXTRACTs legal ...

As far as I can tell legalization of weird sizes for the
output type isn't implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326714 91177308-0d34-0410-b5e6-96231b3b80d8

2018-03-05 16:25:15 +00:00

..

AArch64

[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.

2018-03-01 22:32:25 +00:00

AMDGPU

AMDGPU/GlobalISel: Make some G_EXTRACTs legal

2018-03-05 16:25:15 +00:00

ARC

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ARM

[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB

2018-03-02 13:02:55 +00:00

AVR

[CodeGen] Unify the syntax of MBB successors in MIR and -debug output

2018-02-09 00:10:31 +00:00

BPF

bpf: New codegen testcases for 32-bit subregister support

2018-02-23 23:49:33 +00:00

Generic

[MergeICmps] Revert 324317 "Enable the MergeICmps Pass by default."

2018-03-02 14:34:49 +00:00

Hexagon

[Hexagon] Generate valignb for shifting shuffles (instead of vdelta)

2018-03-02 22:22:19 +00:00

Inputs

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Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[TLS] use emulated TLS if the target supports only this mode

2018-02-28 17:48:55 +00:00

MIR

[MIRParser] Accept overloaded intrinsic names w/o type suffixes

2018-02-28 23:51:49 +00:00

MSP430

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.

2018-03-01 22:32:25 +00:00

PowerPC

[MergeICmps] Revert 324317 "Enable the MergeICmps Pass by default."

2018-03-02 14:34:49 +00:00

RISCV

[RISCV] Update two tests after r326208

2018-02-28 08:20:47 +00:00

SPARC

Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"

2018-02-27 16:59:10 +00:00

SystemZ

[SystemZ] Fix test cases after r326613

2018-03-02 21:22:42 +00:00

Thumb

[ARM] Fix access to stack arguments when re-aligning SP in Armv6m

2018-03-02 15:47:14 +00:00

Thumb2

ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

2018-02-27 19:00:59 +00:00

WebAssembly

[WebAssembly] Add mechanisms for specifying an explicit import module name.

2018-02-09 23:13:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

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X86

[X86] Add a DAG combine to turn stores of vXi1 constants into scalar stores.

2018-03-04 19:33:15 +00:00

XCore

[XCore] Return true in enableMultipleCopyHints().

2018-02-26 08:03:32 +00:00