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Eli Friedman ffd5316983 [ARM] VFPv2 only supports 16 D registers.

r361845 changed the way we handle "D16" vs. "D32" targets; there used to
be a negative "d16" which removed instructions from the instruction set,
and now there's a "d32" feature which adds instructions to the
instruction set.  This is good, but there was an oversight in the
implementation: the behavior of VFPv2 was changed.  In particular, the
"vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only
supports 16 D registers.

In practice, this means if you specify -mfpu=vfpv2, the compiler will
generate illegal instructions.

This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and
"vfp2sp" so they don't imply "d32".

Differential Revision: https://reviews.llvm.org/D67375



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372186 91177308-0d34-0410-b5e6-96231b3b80d8

2019-09-17 21:42:38 +00:00

AArch64

[AArch64][GlobalISel] Support -tailcallopt

2019-09-17 20:24:23 +00:00

AMDGPU

[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed

2019-09-17 09:08:58 +00:00

ARC

…

ARM

[ARM] VFPv2 only supports 16 D registers.

2019-09-17 21:42:38 +00:00