Quentin Colombet ce22b10a6e [RegisterBankInfo] Uniquely allocate instruction mapping. ...

This is a step toward having statically allocated instruciton mapping.
We are going to tablegen them eventually, so let us reflect that in
the API.

NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302316 91177308-0d34-0410-b5e6-96231b3b80d8

2017-05-05 22:48:22 +00:00

..

CallLowering.cpp

[IR] Abstract away ArgNo+1 attribute indexing as much as possible

2017-05-03 18:17:31 +00:00

CMakeLists.txt

Revert "Localizer fun"

2017-04-01 01:26:21 +00:00

GlobalISel.cpp

Revert "Localizer fun"

2017-04-01 01:26:21 +00:00

InstructionSelect.cpp

ARM: Compute MaxCallFrame size early

2017-05-05 22:04:05 +00:00

InstructionSelector.cpp

[globalisel][tablegen] Compute available feature bits correctly.

2017-04-29 17:30:09 +00:00

IRTranslator.cpp

ARM: Compute MaxCallFrame size early

2017-05-05 22:04:05 +00:00

Legalizer.cpp

[GISel]:Skip legalizing Intermediate inst(with generic types)

2017-05-04 22:00:42 +00:00

LegalizerHelper.cpp

[GlobalISel] Legalize G_(S|U)DIV libcalls

2017-04-24 07:22:31 +00:00

LegalizerInfo.cpp

[GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types

2017-04-11 10:10:14 +00:00

LLVMBuild.txt

Revert "Get GlobalISel to build on Linux after r286407"

2016-11-16 22:24:59 +00:00

MachineIRBuilder.cpp

[GlobalISel] Support vector-of-pointers in LLT

2017-04-19 07:23:57 +00:00

RegBankSelect.cpp

[RegisterBankInfo] Uniquely allocate instruction mapping.

2017-05-05 22:48:22 +00:00

RegisterBank.cpp

Move size and alignment information of regclass to TargetRegisterInfo

2017-04-24 18:55:33 +00:00

RegisterBankInfo.cpp

[RegisterBankInfo] Uniquely allocate instruction mapping.

2017-05-05 22:48:22 +00:00

Utils.cpp

[GISEL]: Move getConstantVReg to Utils

2017-04-19 20:48:50 +00:00