Tim Northover 464549ab4d ARM: fix handling of SUB immediates in peephole opt. ...

We were negating an immediate that was going to be used in a SUBri form
unnecessarily. Since ADD/SUB are very similar we *can* do that, but we have to
change the SUB to an ADD at the same time. This also applies to ADD, and allows
us to handle a slightly larger range of immediates for those two operations.

rdar://25992245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268276 91177308-0d34-0410-b5e6-96231b3b80d8

2016-05-02 18:30:08 +00:00

..

ARMLoadStoreDBG.mir

tests: tweak MIR for ARM tests to correct MI issues

2016-04-26 17:54:21 +00:00

bundled-instructions.mir

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

cfi-same-value.mir

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

expected-closing-brace.mir

MIR Serialization: Serialize the bundled machine instructions.

2015-08-14 18:57:24 +00:00

extraneous-closing-brace-error.mir

MIR Serialization: Serialize the bundled machine instructions.

2015-08-14 18:57:24 +00:00

imm-peephole-arm.mir

ARM: fix handling of SUB immediates in peephole opt.

2016-05-02 18:30:08 +00:00

imm-peephole-thumb.mir

ARM: fix handling of SUB immediates in peephole opt.

2016-05-02 18:30:08 +00:00

lit.local.cfg

MIR Serialization: Serialize the bundled machine instructions.

2015-08-14 18:57:24 +00:00

nested-instruction-bundle-error.mir

MIR Serialization: Serialize the bundled machine instructions.

2015-08-14 18:57:24 +00:00

sched-it-debug-nodes.mir

tests: tweak MIR for ARM tests to correct MI issues

2016-04-26 17:54:21 +00:00