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af9296a79c
Summary: LegalizerInfo assumes all G_MERGE_VALUES and G_UNMERGE_VALUES instructions are legal, so it is not possible to legalize vector operations on illegal vector types. This patch fixes the problem by removing the related check and adding default actions for G_MERGE_VALUES and G_UNMERGE_VALUES. Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, t.p.northover, kristof.beyls Reviewed By: dsanders Subscribers: rovka, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39823 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319524 91177308-0d34-0410-b5e6-96231b3b80d8
412 lines
16 KiB
C++
412 lines
16 KiB
C++
//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMLegalizerInfo.h"
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#include "ARMCallLowering.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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using namespace llvm;
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/// FIXME: The following static functions are SizeChangeStrategy functions
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/// that are meant to temporarily mimic the behaviour of the old legalization
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/// based on doubling/halving non-legal types as closely as possible. This is
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/// not entirly possible as only legalizing the types that are exactly a power
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/// of 2 times the size of the legal types would require specifying all those
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/// sizes explicitly.
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/// In practice, not specifying those isn't a problem, and the below functions
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/// should disappear quickly as we add support for legalizing non-power-of-2
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/// sized types further.
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static void
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addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
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const LegalizerInfo::SizeAndActionsVec &v) {
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for (unsigned i = 0; i < v.size(); ++i) {
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result.push_back(v[i]);
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if (i + 1 < v[i].first && i + 1 < v.size() &&
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v[i + 1].first != v[i].first + 1)
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result.push_back({v[i].first + 1, LegalizerInfo::Unsupported});
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}
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}
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static LegalizerInfo::SizeAndActionsVec
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widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
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assert(v.size() >= 1);
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assert(v[0].first > 17);
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LegalizerInfo::SizeAndActionsVec result = {
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{1, LegalizerInfo::Unsupported},
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{8, LegalizerInfo::WidenScalar}, {9, LegalizerInfo::Unsupported},
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{16, LegalizerInfo::WidenScalar}, {17, LegalizerInfo::Unsupported}};
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addAndInterleaveWithUnsupported(result, v);
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auto Largest = result.back().first;
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result.push_back({Largest + 1, LegalizerInfo::Unsupported});
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return result;
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}
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static LegalizerInfo::SizeAndActionsVec
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widen_1_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
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assert(v.size() >= 1);
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assert(v[0].first > 17);
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LegalizerInfo::SizeAndActionsVec result = {
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{1, LegalizerInfo::WidenScalar}, {2, LegalizerInfo::Unsupported},
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{8, LegalizerInfo::WidenScalar}, {9, LegalizerInfo::Unsupported},
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{16, LegalizerInfo::WidenScalar}, {17, LegalizerInfo::Unsupported}};
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addAndInterleaveWithUnsupported(result, v);
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auto Largest = result.back().first;
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result.push_back({Largest + 1, LegalizerInfo::Unsupported});
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return result;
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}
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static bool AEABI(const ARMSubtarget &ST) {
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return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
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}
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ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT p0 = LLT::pointer(0, 32);
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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setAction({G_GLOBAL_VALUE, p0}, Legal);
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setAction({G_FRAME_INDEX, p0}, Legal);
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for (unsigned Op : {G_LOAD, G_STORE}) {
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for (auto Ty : {s1, s8, s16, s32, p0})
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setAction({Op, Ty}, Legal);
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setAction({Op, 1, p0}, Legal);
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}
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for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
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if (Op != G_ADD)
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setLegalizeScalarToDifferentSizeStrategy(
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Op, 0, widenToLargerTypesUnsupportedOtherwise);
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setAction({Op, s32}, Legal);
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}
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for (unsigned Op : {G_SDIV, G_UDIV}) {
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setLegalizeScalarToDifferentSizeStrategy(Op, 0,
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widenToLargerTypesUnsupportedOtherwise);
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Legal);
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else
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setAction({Op, s32}, Libcall);
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}
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for (unsigned Op : {G_SREM, G_UREM}) {
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setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Lower);
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else if (AEABI(ST))
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setAction({Op, s32}, Custom);
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else
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setAction({Op, s32}, Libcall);
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}
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for (unsigned Op : {G_SEXT, G_ZEXT, G_ANYEXT}) {
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setAction({Op, s32}, Legal);
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}
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for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
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setAction({Op, s32}, Legal);
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s32}, Legal);
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setAction({G_SELECT, s32}, Legal);
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setAction({G_SELECT, p0}, Legal);
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setAction({G_SELECT, 1, s1}, Legal);
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setAction({G_BRCOND, s1}, Legal);
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setAction({G_CONSTANT, s32}, Legal);
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setLegalizeScalarToDifferentSizeStrategy(G_CONSTANT, 0, widen_1_8_16);
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setAction({G_ICMP, s1}, Legal);
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setLegalizeScalarToDifferentSizeStrategy(G_ICMP, 1,
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widenToLargerTypesUnsupportedOtherwise);
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for (auto Ty : {s32, p0})
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setAction({G_ICMP, 1, Ty}, Legal);
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if (!ST.useSoftFloat() && ST.hasVFP2()) {
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for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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for (auto Ty : {s32, s64})
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setAction({BinOp, Ty}, Legal);
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setAction({G_LOAD, s64}, Legal);
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setAction({G_STORE, s64}, Legal);
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setAction({G_FCMP, s1}, Legal);
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setAction({G_FCMP, 1, s32}, Legal);
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setAction({G_FCMP, 1, s64}, Legal);
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} else {
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for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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for (auto Ty : {s32, s64})
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setAction({BinOp, Ty}, Libcall);
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setAction({G_FCMP, s1}, Legal);
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setAction({G_FCMP, 1, s32}, Custom);
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setAction({G_FCMP, 1, s64}, Custom);
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if (AEABI(ST))
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setFCmpLibcallsAEABI();
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else
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setFCmpLibcallsGNU();
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}
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for (unsigned Op : {G_FREM, G_FPOW})
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for (auto Ty : {s32, s64})
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setAction({Op, Ty}, Libcall);
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// Merge/Unmerge
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for (const auto &Ty : {s32, s64}) {
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setAction({G_MERGE_VALUES, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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for (const auto &Ty : {s16, s32}) {
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setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, Ty}, Legal);
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}
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computeTables();
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}
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void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {
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{RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {
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{RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
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{RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OGE] = {
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{RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OGT] = {
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{RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OLE] = {
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{RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OLT] = {
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{RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UNO] = {
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{RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_ONE] = {
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{RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
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{RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
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}
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void ARMLegalizerInfo::setFCmpLibcallsGNU() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
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{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
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{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
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FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
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FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
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FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
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FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
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FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
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FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
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FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
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FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
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{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
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{RTLIB::UO_F64, CmpInst::ICMP_NE}};
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}
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ARMLegalizerInfo::FCmpLibcallsList
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ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
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unsigned Size) const {
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assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
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if (Size == 32)
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return FCmp32Libcalls[Predicate];
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if (Size == 64)
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return FCmp64Libcalls[Predicate];
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llvm_unreachable("Unsupported size for FCmp predicate");
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}
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bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return false;
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case G_SREM:
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case G_UREM: {
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unsigned OriginalResult = MI.getOperand(0).getReg();
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auto Size = MRI.getType(OriginalResult).getSizeInBits();
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if (Size != 32)
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return false;
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auto Libcall =
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MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
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// Our divmod libcalls return a struct containing the quotient and the
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// remainder. We need to create a virtual register for it.
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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Type *ArgTy = Type::getInt32Ty(Ctx);
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StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
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auto RetVal = MRI.createGenericVirtualRegister(
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getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
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auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
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{{MI.getOperand(1).getReg(), ArgTy},
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{MI.getOperand(2).getReg(), ArgTy}});
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if (Status != LegalizerHelper::Legalized)
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return false;
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// The remainder is the second result of divmod. Split the return value into
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// a new, unused register for the quotient and the destination of the
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// original instruction for the remainder.
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MIRBuilder.buildUnmerge(
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{MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
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RetVal);
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break;
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}
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case G_FCMP: {
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assert(MRI.getType(MI.getOperand(2).getReg()) ==
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MRI.getType(MI.getOperand(3).getReg()) &&
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"Mismatched operands for G_FCMP");
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auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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auto OriginalResult = MI.getOperand(0).getReg();
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auto Predicate =
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
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|
|
if (Libcalls.empty()) {
|
|
assert((Predicate == CmpInst::FCMP_TRUE ||
|
|
Predicate == CmpInst::FCMP_FALSE) &&
|
|
"Predicate needs libcalls, but none specified");
|
|
MIRBuilder.buildConstant(OriginalResult,
|
|
Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
|
|
assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
|
|
auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
|
|
auto *RetTy = Type::getInt32Ty(Ctx);
|
|
|
|
SmallVector<unsigned, 2> Results;
|
|
for (auto Libcall : Libcalls) {
|
|
auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
auto Status =
|
|
createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
|
|
{{MI.getOperand(2).getReg(), ArgTy},
|
|
{MI.getOperand(3).getReg(), ArgTy}});
|
|
|
|
if (Status != LegalizerHelper::Legalized)
|
|
return false;
|
|
|
|
auto ProcessedResult =
|
|
Libcalls.size() == 1
|
|
? OriginalResult
|
|
: MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
|
|
|
|
// We have a result, but we need to transform it into a proper 1-bit 0 or
|
|
// 1, taking into account the different peculiarities of the values
|
|
// returned by the comparison functions.
|
|
CmpInst::Predicate ResultPred = Libcall.Predicate;
|
|
if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
|
|
// We have a nice 0 or 1, and we just need to truncate it back to 1 bit
|
|
// to keep the types consistent.
|
|
MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
|
|
} else {
|
|
// We need to compare against 0.
|
|
assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
|
|
auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MIRBuilder.buildConstant(Zero, 0);
|
|
MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
|
|
}
|
|
Results.push_back(ProcessedResult);
|
|
}
|
|
|
|
if (Results.size() != 1) {
|
|
assert(Results.size() == 2 && "Unexpected number of results");
|
|
MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|