archived-llvm

mirror of https://github.com/RPCS3/llvm.git synced 2026-01-31 01:25:19 +01:00

Files

Mikael Holmen 78cae93022 Skip DBG instr in OptimizePHIs when looking for dead PHI cycles

Summary:
Changed use_instructions() to use_nodbg_instructions() when
building an instruction set.

We don't want the presence of debug info to affect the code
we generate.

Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl

Reviewed By: aprantl

Subscribers: aprantl, llvm-commits

Differential Revision: https://reviews.llvm.org/D40882

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320010 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-07 07:01:21 +00:00

AArch64

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

AMDGPU

MIR: Print the register class or bank in vreg defs

2017-10-24 18:04:54 +00:00

ARM

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Generic

[RegAllocFast] Add the proper initialize method to use the .mir infrastructure

2017-07-07 19:25:42 +00:00

Hexagon

[Hexagon] Handle Hexagon-specific machine operand target flags in MIR

2017-07-10 18:31:02 +00:00

Mips

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

NVPTX

MIR: Print the register class or bank in vreg defs

2017-10-24 18:04:54 +00:00

PowerPC

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

X86

Skip DBG instr in OptimizePHIs when looking for dead PHI cycles

2017-12-07 07:01:21 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.