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ca0df55065
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
3.5 KiB
LLVM
135 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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define i32 @udiv(i32 %a, i32 %b) {
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; RV32I-LABEL: udiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a2, %hi(__udivsi3)
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; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
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; RV32I-NEXT: jalr ra, a2, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = udiv i32 %a, %b
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ret i32 %1
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}
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define i32 @udiv_constant(i32 %a) {
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; RV32I-LABEL: udiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a1, %hi(__udivsi3)
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; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: jalr ra, a2, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = udiv i32 %a, 5
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ret i32 %1
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}
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define i32 @udiv_pow2(i32 %a) {
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; RV32I-LABEL: udiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 3
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = udiv i32 %a, 8
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ret i32 %1
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}
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define i64 @udiv64(i64 %a, i64 %b) {
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; RV32I-LABEL: udiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a4, %hi(__udivdi3)
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; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
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; RV32I-NEXT: jalr ra, a4, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = udiv i64 %a, %b
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ret i64 %1
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}
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define i64 @udiv64_constant(i64 %a) {
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; RV32I-LABEL: udiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a2, %hi(__udivdi3)
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; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: addi a3, zero, 0
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; RV32I-NEXT: jalr ra, a4, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = udiv i64 %a, 5
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ret i64 %1
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}
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define i32 @sdiv(i32 %a, i32 %b) {
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; RV32I-LABEL: sdiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a2, %hi(__divsi3)
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; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
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; RV32I-NEXT: jalr ra, a2, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sdiv i32 %a, %b
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ret i32 %1
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}
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define i32 @sdiv_constant(i32 %a) {
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; RV32I-LABEL: sdiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a1, %hi(__divsi3)
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; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: jalr ra, a2, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sdiv i32 %a, 5
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ret i32 %1
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}
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define i32 @sdiv_pow2(i32 %a) {
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; RV32I-LABEL: sdiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: srli a1, a1, 29
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srai a0, a0, 3
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sdiv i32 %a, 8
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ret i32 %1
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}
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define i64 @sdiv64(i64 %a, i64 %b) {
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; RV32I-LABEL: sdiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a4, %hi(__divdi3)
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; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
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; RV32I-NEXT: jalr ra, a4, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sdiv i64 %a, %b
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ret i64 %1
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}
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define i64 @sdiv64_constant(i64 %a) {
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; RV32I-LABEL: sdiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw ra, 12(s0)
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; RV32I-NEXT: lui a2, %hi(__divdi3)
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; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: addi a3, zero, 0
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; RV32I-NEXT: jalr ra, a4, 0
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; RV32I-NEXT: lw ra, 12(s0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sdiv i64 %a, 5
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ret i64 %1
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}
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