Tim Northover f4523b0efd ARM: avoid clobbering register in v6 jump-table expansion. ...

If we got unlucky with register allocation and actual constpool placement, we
could end up producing a tTBB_JT with an index that's already been clobbered.

Technically, we might be able to fix this situation up with a MOV, but I think
the constant islands pass is complex enough without having to deal with more
weird edge-cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297871 91177308-0d34-0410-b5e6-96231b3b80d8

2017-03-15 18:38:13 +00:00

..

CMakeLists.txt

[CMake] NFC. Updating CMake dependency specifications

2016-11-17 04:36:50 +00:00

LLVMBuild.txt

MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum().

2015-07-24 01:12:36 +00:00

MILexer.cpp

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

MILexer.h

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

MIParser.cpp

MIR: parse & print the atomic parts of a MachineMemOperand.

2017-02-13 22:14:08 +00:00

MIParser.h

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00

MIRParser.cpp

ARM: avoid clobbering register in v6 jump-table expansion.

2017-03-15 18:38:13 +00:00