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abc1d2159c72293bcb18a2ec00da6bc210ddc52b
archived-llvm/lib/Target/AMDGPU
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Konstantin Zhuravlyov f9bcd7b189 [AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions 
Differential Revision: https://reviews.llvm.org/D24125



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282624 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-28 20:05:39 +00:00
..
AsmParser
[AMDGPU][mc] Add support for absolute expressions in DPP modifiers.
2016-09-22 11:47:21 +00:00
Disassembler
Revert "[AMDGPU] Disassembler: print label names in branch instructions"
2016-09-26 11:29:03 +00:00
InstPrinter
[AMDGPU] Enable changing instprinter's behavior based on the per-function
2016-09-27 14:42:48 +00:00
MCTargetDesc
[AMDGPU] Assembler: remove unused AMDGPUMCObjectWriter.
2016-09-21 10:33:32 +00:00
TargetInfo
Remove autoconf support
2016-01-26 21:29:08 +00:00
Utils
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
AMDGPU.h
AMDGPU: Split SILowerControlFlow into two pieces
2016-08-22 19:33:16 +00:00
AMDGPU.td
[AMDGPU] Enable changing instprinter's behavior based on the per-function
2016-09-27 14:42:48 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU/SI: Handle aliases in AMDGPUAlwaysInlinePass
2016-08-31 11:18:33 +00:00
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
AMDGPUAnnotateUniformValues.cpp
Add optimization bisect opt-in calls for AMDGPU passes
2016-04-25 22:23:44 +00:00
AMDGPUAsmPrinter.cpp
AMDGPU/SI: Don't crash on anonymous GlobalValues
2016-09-26 17:29:25 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
AMDGPUCallingConv.td
AMDGPU: Fix kernel argument alignment impacting stack size
2016-06-18 05:15:53 +00:00
AMDGPUCallLowering.cpp
GlobalISel: pass Function to lowerFormalArguments directly (NFC).
2016-09-21 12:57:35 +00:00
AMDGPUCallLowering.h
GlobalISel: pass Function to lowerFormalArguments directly (NFC).
2016-09-21 12:57:35 +00:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions
2016-09-28 20:05:39 +00:00
AMDGPUFrameLowering.cpp
MachineFunction: Return reference for getFrameInfo(); NFC
2016-07-28 18:40:00 +00:00
AMDGPUFrameLowering.h
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
AMDGPUInstrInfo.cpp
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
AMDGPUInstrInfo.h
AMDGPU/R600: Remove macros
2016-08-13 01:43:46 +00:00
AMDGPUInstrInfo.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
AMDGPUInstructions.td
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPU: Change fdiv lowering based on !fpmath metadata
2016-07-19 23:16:53 +00:00
AMDGPUIntrinsicInfo.h
AMDGPU: Change fdiv lowering based on !fpmath metadata
2016-07-19 23:16:53 +00:00
AMDGPUIntrinsics.td
AMDGPU: Remove read_workdim intrinsic
2016-07-25 20:17:02 +00:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Fix broken FrameIndex handling
2016-09-17 16:09:55 +00:00
AMDGPUISelLowering.cpp
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
2016-09-28 16:37:50 +00:00
AMDGPUISelLowering.h
AMDGPU: Refactor kernel argument lowering
2016-09-16 21:53:00 +00:00
AMDGPUMachineFunction.cpp
AMDGPU: Make AMDGPUMachineFunction fields private
2016-07-26 16:45:58 +00:00
AMDGPUMachineFunction.h
AMDGPU: Make AMDGPUMachineFunction fields private
2016-07-26 16:45:58 +00:00
AMDGPUMCInstLower.cpp
AMDGPU/SI: Don't crash on anonymous GlobalValues
2016-09-26 17:29:25 +00:00
AMDGPUMCInstLower.h
AMDGPU/SI: Don't crash on anonymous GlobalValues
2016-09-26 17:29:25 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
[NFC] Header cleanup
2016-04-18 09:17:29 +00:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
AMDGPURegisterInfo.cpp
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
AMDGPURegisterInfo.h
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
AMDGPURegisterInfo.td
AMDGPU: Set SubRegIndex size and offset
2015-07-30 17:03:11 +00:00
AMDGPURuntimeMetadata.h
AMDGPU: Add hidden kernel arguments to runtime metadata
2016-09-07 17:44:00 +00:00
AMDGPUSubtarget.cpp
AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_size
2016-09-23 01:33:26 +00:00
AMDGPUSubtarget.h
AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_size
2016-09-23 01:33:26 +00:00
AMDGPUTargetMachine.cpp
AMDGPU: Run LoadStoreVectorizer pass by default
2016-09-09 22:29:28 +00:00
AMDGPUTargetMachine.h
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
AMDGPUTargetObjectFile.cpp
Move the Mangler from the AsmPrinter down to TLOF and clean up the
2016-09-16 07:33:15 +00:00
AMDGPUTargetObjectFile.h
Move the Mangler from the AsmPrinter down to TLOF and clean up the
2016-09-16 07:33:15 +00:00
AMDGPUTargetTransformInfo.cpp
AMDGPU: Implement getLoadStoreVecRegBitWidth
2016-07-01 00:56:27 +00:00
AMDGPUTargetTransformInfo.h
[TTI] The cost model should not assume vector casts get completely scalarized
2016-07-06 17:30:56 +00:00
AMDILCFGStructurizer.cpp
CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
2016-08-24 01:52:46 +00:00
AMDKernelCodeT.h
[AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields)
2016-02-24 10:54:25 +00:00
BUFInstructions.td
[AMDGPU] Fix for bz30427: wrong MTBUF encoding on VI
2016-09-23 21:21:21 +00:00
CaymanInstructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
CIInstructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
CMakeLists.txt
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
DSInstructions.td
[AMDGPU][mc] Add support for ds_add_[rtn_]f32.
2016-09-21 16:35:44 +00:00
EvergreenInstructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
FLATInstructions.td
[AMDGPU] Refactor FLAT TD instructions
2016-09-05 11:22:51 +00:00
GCNHazardRecognizer.cpp
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
GCNHazardRecognizer.h
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
GCNSchedStrategy.cpp
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
GCNSchedStrategy.h
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
LLVMBuild.txt
AMDGPU: Prune AMDGPUAsmParser in libdeps.
2016-07-09 07:54:27 +00:00
MIMGInstructions.td
AMDGPU/SI: MIMG TD Refactoring.
2016-09-01 17:54:54 +00:00
Processors.td
AMDGPU : Add XNACK feature to GPUs that support it.
2016-09-06 19:55:17 +00:00
R600ClauseMergePass.cpp
AMDGPU: Remove implicit iterator conversions, NFC
2016-07-08 19:16:05 +00:00
R600ControlFlowFinalizer.cpp
AMDGPU: Avoid looking for the DebugLoc in end()
2016-08-17 00:06:43 +00:00
R600Defines.h
AMDGPU: R600 code splitting cleanup
2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp
Fix more dereferenced end() iterators after r278532
2016-08-13 01:12:49 +00:00
R600ExpandSpecialInstrs.cpp
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
R600FrameLowering.cpp
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
R600FrameLowering.h
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
R600InstrFormats.td
AMDGPU/R600: Convert buffer id to VTX_READ input
2016-08-15 21:38:30 +00:00
R600InstrInfo.cpp
Finish renaming remaining analyzeBranch functions
2016-09-14 20:43:16 +00:00
R600InstrInfo.h
Finish renaming remaining analyzeBranch functions
2016-09-14 20:43:16 +00:00
R600Instructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
R600Intrinsics.td
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics
2016-07-15 21:27:08 +00:00
R600ISelLowering.cpp
AMDGPU: Refactor kernel argument lowering
2016-09-16 21:53:00 +00:00
R600ISelLowering.h
AMDGPU: Fix i1 fp_to_int
2016-07-22 17:01:21 +00:00
R600MachineFunctionInfo.cpp
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
R600MachineFunctionInfo.h
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
R600MachineScheduler.cpp
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
2016-06-30 00:01:54 +00:00
R600MachineScheduler.h
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
R600OptimizeVectorRegisters.cpp
Use the range variant of find instead of unpacking begin/end
2016-08-11 22:21:41 +00:00
R600Packetizer.cpp
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
2016-06-30 00:01:54 +00:00
R600RegisterInfo.cpp
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
R600RegisterInfo.h
AMDGPU: Move R600 only pieces into R600 classes
2016-07-09 18:11:15 +00:00
R600RegisterInfo.td
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
R600Schedule.td
AMDGPU: Fix trailing whitespace
2016-06-10 02:18:02 +00:00
R700Instructions.td
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
SIAnnotateControlFlow.cpp
AMDGPU: Allow some control flow intrinsics to be CSEd
2016-09-16 22:11:18 +00:00
SIDebuggerInsertNops.cpp
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
SIDefines.h
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SIFixControlFlowLiveIntervals.cpp
Revert "AMDGPU: Remove unused control flow intrinsic"
2016-07-09 17:18:39 +00:00
SIFixSGPRCopies.cpp
Revert "AMDGPU: Remove unused control flow intrinsic"
2016-07-09 17:18:39 +00:00
SIFoldOperands.cpp
AMDGPU: Support folding FrameIndex operands
2016-09-14 15:51:33 +00:00
SIFrameLowering.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
SIFrameLowering.h
AMDGPU: Refactor frame lowering
2016-08-31 21:52:21 +00:00
SIInsertSkips.cpp
AMDGPU: Split SILowerControlFlow into two pieces
2016-08-22 19:33:16 +00:00
SIInsertWaits.cpp
AMDGPU: Remove implicit iterator conversions, NFC
2016-07-08 19:16:05 +00:00
SIInstrFormats.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
SIInstrInfo.cpp
AMDGPU: Use i64 scalar compare instructions
2016-09-17 02:02:19 +00:00
SIInstrInfo.h
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SIInstrInfo.td
Revert "[AMDGPU] Disassembler: print label names in branch instructions"
2016-09-26 11:29:03 +00:00
SIInstructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
SIIntrinsics.td
AMDGPU: Allow some control flow intrinsics to be CSEd
2016-09-16 22:11:18 +00:00
SIISelLowering.cpp
[AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions
2016-09-28 20:05:39 +00:00
SIISelLowering.h
AMDGPU: Fix broken FrameIndex handling
2016-09-17 16:09:55 +00:00
SILoadStoreOptimizer.cpp
SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused-variable]
2016-08-30 11:50:21 +00:00
SILowerControlFlow.cpp
AMDGPU: Remove register operand from si_mask_branch
2016-08-27 00:42:21 +00:00
SILowerI1Copies.cpp
AMDGPU: Cleanup subtarget handling.
2016-06-24 06:30:11 +00:00
SIMachineFunctionInfo.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
SIMachineFunctionInfo.h
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
SIMachineScheduler.cpp
AMDGPU/SI: Use a better method for determining the largest pressure sets
2016-08-26 21:16:37 +00:00
SIMachineScheduler.h
AMDGPU: R600 code splitting cleanup
2016-03-11 08:00:27 +00:00
SIRegisterInfo.cpp
AMDGPU: Rename spill operands to match real instruction
2016-09-17 15:52:37 +00:00
SIRegisterInfo.h
Remove unnecessary call to getAllocatableRegClass
2016-09-07 06:16:45 +00:00
SIRegisterInfo.td
AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.
2016-09-09 19:31:51 +00:00
SISchedule.td
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
SIShrinkInstructions.cpp
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SITypeRewriter.cpp
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
SIWholeQuadMode.cpp
AMDGPU: Do not clobber SCC in SIWholeQuadMode
2016-09-12 16:25:20 +00:00
SMInstructions.td
[AMDGPU] Scalar Memory instructions TD refactoring
2016-09-01 09:56:47 +00:00
SOPInstructions.td
AMDGPU: Use i64 scalar compare instructions
2016-09-17 02:02:19 +00:00
VIInstrFormats.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VIInstructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VOP1Instructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VOP2Instructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VOP3Instructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VOPCInstructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VOPInstructions.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00