Geoff Berry dcf371dfad [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg(). ...

Summary:
The current implementation of isConstantPhysReg() checks for defs of
physical registers to determine if they are constant.  Some
architectures (e.g. AArch64 XZR/WZR) have registers that are constant
and may be used as destinations to indicate the generated value is
discarded, preventing isConstantPhysReg() from returning true.  This
change adds a TargetRegisterInfo hook that overrides the no defs check
for cases such as this.

Reviewers: MatzeB, qcolombet, t.p.northover, jmolloy

Subscribers: junbuml, aemerson, mcrosier, rengolin

Differential Revision: https://reviews.llvm.org/D24570

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282543 91177308-0d34-0410-b5e6-96231b3b80d8

2016-09-27 22:17:27 +00:00

..

AArch64

[TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().

2016-09-27 22:17:27 +00:00

AMDGPU

GlobalISel: move type information to MachineRegisterInfo.

2016-09-09 11:46:34 +00:00

ARM

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

Generic

MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it

2016-08-24 22:34:06 +00:00

Hexagon

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

Lanai

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

Mips

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

NVPTX

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

PowerPC

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

X86

GlobalISel: disambiguate types when printing MIR

2016-09-12 11:20:10 +00:00