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archived-llvm/test/CodeGen/ARM
Weiming Zhao 298455f377 [Cortex-M0] Atomic lowering
Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls.

Reviewers: rengolin, efriedma, t.p.northover, jmolloy

Subscribers: efriedma, aemerson, llvm-commits

Differential Revision: https://reviews.llvm.org/D26120

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285969 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-03 21:49:08 +00:00
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