Files
archived-llvm/test/CodeGen
Simon Pilgrim b03ba30cbf [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectors
SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285123 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-25 21:20:18 +00:00
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2016-10-19 16:58:59 +00:00
2016-10-19 15:55:11 +00:00