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archived-llvm/test/Transforms/InstSimplify
Philip Reames 49a006cd8d [InstSimplify] sgt on i1s also encodes implication
Follow on to http://reviews.llvm.org/D13074, implementing something pointed out by Sanjoy. His truth table from his comment on that bug summarizes things well:
LHS | RHS | LHS >=s RHS | LHS implies RHS
0 | 0 | 1 (0 >= 0) | 1
0 | 1 | 1 (0 >= -1) | 1
1 | 0 | 0 (-1 >= 0) | 0
1 | 1 | 1 (-1 >= -1) | 1

The key point is that an "i1 1" is the value "-1", not "1".

Differential Revision: http://reviews.llvm.org/D13756



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251597 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-29 03:19:10 +00:00
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