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eb3fd4c932
At the point when we perform `emitTransformedIndex`, we have a broken IR (in particular, we have Phis for which not every incoming value is properly set). On such IR, it is illegal to create SCEV expressions, because their internal simplification process may try to prove some predicates and break when it stumbles across some broken IR. The only purpose of using SCEV in this particular place is attempt to simplify the generated code slightly. It seems that the result isn't worth it, because some trivial cases (like addition of zero and multiplication by 1) can be handled separately if needed, but more generally InstCombine is able to achieve the goals we want to achieve by using SCEV. This patch fixes a functional crash described in PR39160, and as side-effect it also generates a bit smarter code in some simple cases. It also may cause some optimality loss (i.e. we will now generate `mul` by power of `2` instead of shift etc), but there is nothing what InstCombine could not handle later. In case of dire need, we can support more trivial cases just in place. Note that this patch only fixes one particular case of the general problem that LV misuses SCEV, attempting to create SCEVs or prove predicates on invalid IR. The general solution, however, seems complex enough. Differential Revision: https://reviews.llvm.org/D52881 Reviewed By: fhahn, hsaito git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343954 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.0 KiB
LLVM
99 lines
3.0 KiB
LLVM
; RUN: opt -loop-vectorize -S < %s 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
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target triple = "x86_64-unknown-linux-gnu"
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; Make sure that we can compile the test without crash.
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define void @barney() {
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; CHECK-LABEL: @barney(
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; CHECK: middle.block:
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bb:
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br label %bb2
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bb2: ; preds = %bb2, %bb
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%tmp4 = icmp slt i32 undef, 0
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br i1 %tmp4, label %bb2, label %bb5
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bb5: ; preds = %bb2
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br label %bb19
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bb18: ; preds = %bb33
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ret void
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bb19: ; preds = %bb36, %bb5
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%tmp21 = phi i64 [ undef, %bb36 ], [ 2, %bb5 ]
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%tmp22 = phi i32 [ %tmp65, %bb36 ], [ undef, %bb5 ]
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br label %bb50
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bb33: ; preds = %bb62
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br i1 undef, label %bb18, label %bb36
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bb36: ; preds = %bb33
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br label %bb19
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bb46: ; preds = %bb50
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br i1 undef, label %bb48, label %bb59
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bb48: ; preds = %bb46
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%tmp49 = add i32 %tmp52, 14
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ret void
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bb50: ; preds = %bb50, %bb19
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%tmp52 = phi i32 [ %tmp55, %bb50 ], [ %tmp22, %bb19 ]
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%tmp53 = phi i64 [ %tmp56, %bb50 ], [ 1, %bb19 ]
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%tmp54 = add i32 %tmp52, 12
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%tmp55 = add i32 %tmp52, 13
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%tmp56 = add nuw nsw i64 %tmp53, 1
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%tmp58 = icmp ult i64 %tmp53, undef
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br i1 %tmp58, label %bb50, label %bb46
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bb59: ; preds = %bb46
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br label %bb62
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bb62: ; preds = %bb68, %bb59
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%tmp63 = phi i32 [ %tmp65, %bb68 ], [ %tmp55, %bb59 ]
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%tmp64 = phi i64 [ %tmp66, %bb68 ], [ %tmp56, %bb59 ]
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%tmp65 = add i32 %tmp63, 13
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%tmp66 = add nuw nsw i64 %tmp64, 1
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%tmp67 = icmp ult i64 %tmp66, %tmp21
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br i1 %tmp67, label %bb68, label %bb33
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bb68: ; preds = %bb62
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br label %bb62
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}
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define i32 @foo(i32 addrspace(1)* %p) {
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; CHECK-LABEL: foo
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; CHECK: middle.block:
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entry:
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br label %outer
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outer: ; preds = %outer_latch, %entry
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%iv = phi i64 [ 2, %entry ], [ %iv.next, %outer_latch ]
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br label %inner
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inner: ; preds = %inner, %outer
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%0 = phi i32 [ %2, %inner ], [ 0, %outer ]
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%a = phi i32 [ %3, %inner ], [ 1, %outer ]
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%b = phi i32 [ %1, %inner ], [ 6, %outer ]
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%1 = add i32 %b, 2
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%2 = or i32 %0, %b
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%3 = add nuw nsw i32 %a, 1
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%4 = zext i32 %3 to i64
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%5 = icmp ugt i64 %iv, %4
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br i1 %5, label %inner, label %outer_latch
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outer_latch: ; preds = %inner
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store atomic i32 %2, i32 addrspace(1)* %p unordered, align 4
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%iv.next = add nuw nsw i64 %iv, 1
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%6 = icmp ugt i64 %iv, 63
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br i1 %6, label %exit, label %outer
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exit: ; preds = %outer_latch
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ret i32 0
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}
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