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8679b1f292
This patch enables generation of NMADD and NMSUB instructions when fneg node is present. These instructions are currently only generated if fsub node is present. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34507 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311862 91177308-0d34-0410-b5e6-96231b3b80d8
290 lines
13 KiB
TableGen
290 lines
13 KiB
TableGen
let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
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def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
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ADDS_FM_MM<0, 0x30>;
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def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
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ADDS_FM_MM<0, 0xf0>;
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def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
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ADDS_FM_MM<0, 0xb0>;
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def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
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ADDS_FM_MM<0, 0x70>;
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def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
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ADDS_FM_MM<1, 0x30>;
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def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
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ADDS_FM_MM<1, 0xf0>;
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def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
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ADDS_FM_MM<1, 0xb0>;
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def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
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ADDS_FM_MM<1, 0x70>;
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def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
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LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
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SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
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LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
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def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
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SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
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def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
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CEQS_FM_MM<0> {
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// FIXME: This is a required to work around the fact that these instructions
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// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
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// fcc register set is used directly.
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bits<3> fcc = 0;
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}
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def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
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CEQS_FM_MM<1> {
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// FIXME: This is a required to work around the fact that these instructions
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// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
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// fcc register set is used directly.
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bits<3> fcc = 0;
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}
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def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
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BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
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def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
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BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
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def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
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ROUND_W_FM_MM<0, 0x24>;
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def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
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ROUND_W_FM_MM<0, 0xec>;
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def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
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ROUND_W_FM_MM<1, 0x6c>;
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def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ROUND_W_FM_MM<1, 0x24>;
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def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
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ROUND_W_FM_MM<1, 0x2c>;
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def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
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ROUND_W_FM_MM<1, 0xec>;
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def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
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ROUND_W_FM_MM<1, 0xac>;
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def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
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fsqrt>, ROUND_W_FM_MM<1, 0x28>;
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def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
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def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
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def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
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ABS_FM_MM<0, 0xd>;
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def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
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ABS_FM_MM<0, 0x1>;
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def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
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ABS_FM_MM<0, 0x2d>;
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def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<0, 0x4d>;
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def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<1, 0x4d>;
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def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABS_FM_MM<0, 0x6d>;
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def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<1, 0x6d>;
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def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
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ABS_FM_MM<1, 0xd>;
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def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
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ABS_FM_MM<1, 0x2d>;
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def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
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ABS_FM_MM<1, 0x1>, FGR_32;
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def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
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II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
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def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
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II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
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def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
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def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
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def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
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MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
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def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
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MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
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def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
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MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
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def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
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MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
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def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
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II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
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def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
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II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
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def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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MADDS_FM_MM<0x1>;
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def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
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MADDS_FM_MM<0x21>;
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def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
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MADDS_FM_MM<0x2>;
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def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
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MADDS_FM_MM<0x22>;
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def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
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MADDS_FM_MM<0x9>;
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def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
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MADDS_FM_MM<0x29>;
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def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
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MADDS_FM_MM<0xa>;
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def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
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MADDS_FM_MM<0x2a>;
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}
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let AdditionalPredicates = [InMicroMips] in {
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def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
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II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
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def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
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FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
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def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
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ROUND_W_FM_MM<0, 0x6c>;
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def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
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fsqrt>, ROUND_W_FM_MM<0, 0x28>;
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def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
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def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
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MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
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let DecoderNamespace = "MicroMips" in {
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def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
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MFC1_FM_MM<0x40>;
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def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
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MFC1_FM_MM<0x60>;
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def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
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II_RECIP_S>,
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ROUND_W_FM_MM<0b0, 0b01001000>;
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def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
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II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
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def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
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II_RECIP_S>,
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ROUND_W_FM_MM<0b0, 0b00001000>;
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def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
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II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
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}
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let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
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def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
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LW_FM_MM<0x2f>, FGR_32 {
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let BaseOpcode = "LDC132";
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}
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def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
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LW_FM_MM<0x2e>, FGR_32;
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def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
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LW_FM_MM<0x27>;
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def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
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LW_FM_MM<0x26>;
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}
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multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
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InstrItinClass itin> {
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def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 0> {
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let BaseOpcode = "c.f."#NAME;
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let isCommutable = 1;
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}
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def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 1> {
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let BaseOpcode = "c.un."#NAME;
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let isCommutable = 1;
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}
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def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 2> {
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let BaseOpcode = "c.eq."#NAME;
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let isCommutable = 1;
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}
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def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 3> {
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let BaseOpcode = "c.ueq."#NAME;
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let isCommutable = 1;
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}
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def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 4> {
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let BaseOpcode = "c.olt."#NAME;
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}
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def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 5> {
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let BaseOpcode = "c.ult."#NAME;
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}
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def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 6> {
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let BaseOpcode = "c.ole."#NAME;
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}
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def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 7> {
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let BaseOpcode = "c.ule."#NAME;
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}
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def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 8> {
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let BaseOpcode = "c.sf."#NAME;
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let isCommutable = 1;
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}
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def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 9> {
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let BaseOpcode = "c.ngle."#NAME;
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}
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def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 10> {
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let BaseOpcode = "c.seq."#NAME;
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let isCommutable = 1;
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}
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def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 11> {
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let BaseOpcode = "c.ngl."#NAME;
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}
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def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 12> {
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let BaseOpcode = "c.lt."#NAME;
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}
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def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 13> {
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let BaseOpcode = "c.nge."#NAME;
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}
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def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 14> {
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let BaseOpcode = "c.le."#NAME;
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}
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def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
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C_COND_FM_MM<fmt, 15> {
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let BaseOpcode = "c.ngt."#NAME;
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}
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}
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defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
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ISA_MIPS1_NOT_32R6_64R6;
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defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
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ISA_MIPS1_NOT_32R6_64R6, FGR_32;
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let DecoderNamespace = "Mips64" in
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defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,
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ISA_MIPS1_NOT_32R6_64R6, FGR_64;
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defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
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ISA_MIPS1_NOT_32R6_64R6;
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defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
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ISA_MIPS1_NOT_32R6_64R6, FGR_32;
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defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
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ISA_MIPS1_NOT_32R6_64R6, FGR_64;
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defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,
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ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
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}
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// To generate NMADD and NMSUB instructions when fneg node is present
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let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, InMicroMips, NotMips32r6] in {
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defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>;
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defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>;
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [InMicroMips] in {
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// Patterns for loads/stores with a reg+imm operand.
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let AddedComplexity = 40 in {
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def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
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def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
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def : LoadRegImmPat<LWC1_MM, f32, load>;
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def : StoreRegImmPat<SWC1_MM, f32>;
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}
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}
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