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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313166 91177308-0d34-0410-b5e6-96231b3b80d8
607 lines
24 KiB
C++
607 lines
24 KiB
C++
//===--------- X86InterleavedAccess.cpp ----------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===--------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the X86 implementation of the interleaved accesses
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/// optimization generating X86-specific instructions/intrinsics for
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/// interleaved access groups.
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///
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//===--------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/VectorUtils.h"
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using namespace llvm;
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namespace {
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/// \brief This class holds necessary information to represent an interleaved
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/// access group and supports utilities to lower the group into
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/// X86-specific instructions/intrinsics.
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/// E.g. A group of interleaving access loads (Factor = 2; accessing every
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/// other element)
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/// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
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/// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
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/// %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
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class X86InterleavedAccessGroup {
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/// \brief Reference to the wide-load instruction of an interleaved access
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/// group.
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Instruction *const Inst;
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/// \brief Reference to the shuffle(s), consumer(s) of the (load) 'Inst'.
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ArrayRef<ShuffleVectorInst *> Shuffles;
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/// \brief Reference to the starting index of each user-shuffle.
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ArrayRef<unsigned> Indices;
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/// \brief Reference to the interleaving stride in terms of elements.
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const unsigned Factor;
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/// \brief Reference to the underlying target.
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const X86Subtarget &Subtarget;
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const DataLayout &DL;
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IRBuilder<> &Builder;
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/// \brief Breaks down a vector \p 'Inst' of N elements into \p NumSubVectors
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/// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
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void decompose(Instruction *Inst, unsigned NumSubVectors, VectorType *T,
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SmallVectorImpl<Instruction *> &DecomposedVectors);
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/// \brief Performs matrix transposition on a 4x4 matrix \p InputVectors and
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/// returns the transposed-vectors in \p TransposedVectors.
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/// E.g.
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/// InputVectors:
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/// In-V0 = p1, p2, p3, p4
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/// In-V1 = q1, q2, q3, q4
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/// In-V2 = r1, r2, r3, r4
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/// In-V3 = s1, s2, s3, s4
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/// OutputVectors:
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/// Out-V0 = p1, q1, r1, s1
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/// Out-V1 = p2, q2, r2, s2
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/// Out-V2 = p3, q3, r3, s3
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/// Out-V3 = P4, q4, r4, s4
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void transpose_4x4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix);
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void interleave8bitStride4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumSubVecElems);
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void deinterleave8bitStride3(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumSubVecElems);
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public:
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/// In order to form an interleaved access group X86InterleavedAccessGroup
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/// requires a wide-load instruction \p 'I', a group of interleaved-vectors
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/// \p Shuffs, reference to the first indices of each interleaved-vector
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/// \p 'Ind' and the interleaving stride factor \p F. In order to generate
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/// X86-specific instructions/intrinsics it also requires the underlying
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/// target information \p STarget.
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explicit X86InterleavedAccessGroup(Instruction *I,
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ArrayRef<ShuffleVectorInst *> Shuffs,
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ArrayRef<unsigned> Ind, const unsigned F,
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const X86Subtarget &STarget,
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IRBuilder<> &B)
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: Inst(I), Shuffles(Shuffs), Indices(Ind), Factor(F), Subtarget(STarget),
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DL(Inst->getModule()->getDataLayout()), Builder(B) {}
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/// \brief Returns true if this interleaved access group can be lowered into
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/// x86-specific instructions/intrinsics, false otherwise.
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bool isSupported() const;
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/// \brief Lowers this interleaved access group into X86-specific
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/// instructions/intrinsics.
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bool lowerIntoOptimizedSequence();
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};
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} // end anonymous namespace
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bool X86InterleavedAccessGroup::isSupported() const {
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VectorType *ShuffleVecTy = Shuffles[0]->getType();
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Type *ShuffleEltTy = ShuffleVecTy->getVectorElementType();
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unsigned ShuffleElemSize = DL.getTypeSizeInBits(ShuffleEltTy);
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unsigned WideInstSize;
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// Currently, lowering is supported for the following vectors:
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// Stride 4:
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// 1. Store and load of 4-element vectors of 64 bits on AVX.
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// 2. Store of 16/32-element vectors of 8 bits on AVX.
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// Stride 3:
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// 1. Load of 16/32-element vecotrs of 8 bits on AVX.
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if (!Subtarget.hasAVX() || (Factor != 4 && Factor != 3))
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return false;
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if (isa<LoadInst>(Inst)) {
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WideInstSize = DL.getTypeSizeInBits(Inst->getType());
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} else
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WideInstSize = DL.getTypeSizeInBits(Shuffles[0]->getType());
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// We support shuffle represents stride 4 for byte type with size of
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// WideInstSize.
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if (ShuffleElemSize == 64 && WideInstSize == 1024 && Factor == 4)
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return true;
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if (ShuffleElemSize == 8 && isa<StoreInst>(Inst) && Factor == 4 &&
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(WideInstSize == 512 || WideInstSize == 1024))
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return true;
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if (ShuffleElemSize == 8 && isa<LoadInst>(Inst) && Factor == 3 &&
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(WideInstSize == 384 || WideInstSize == 768))
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return true;
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return false;
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}
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void X86InterleavedAccessGroup::decompose(
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Instruction *VecInst, unsigned NumSubVectors, VectorType *SubVecTy,
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SmallVectorImpl<Instruction *> &DecomposedVectors) {
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assert((isa<LoadInst>(VecInst) || isa<ShuffleVectorInst>(VecInst)) &&
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"Expected Load or Shuffle");
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Type *VecTy = VecInst->getType();
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(void)VecTy;
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assert(VecTy->isVectorTy() &&
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DL.getTypeSizeInBits(VecTy) >=
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DL.getTypeSizeInBits(SubVecTy) * NumSubVectors &&
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"Invalid Inst-size!!!");
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if (auto *SVI = dyn_cast<ShuffleVectorInst>(VecInst)) {
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Value *Op0 = SVI->getOperand(0);
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Value *Op1 = SVI->getOperand(1);
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// Generate N(= NumSubVectors) shuffles of T(= SubVecTy) type.
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for (unsigned i = 0; i < NumSubVectors; ++i)
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DecomposedVectors.push_back(
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cast<ShuffleVectorInst>(Builder.CreateShuffleVector(
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Op0, Op1,
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createSequentialMask(Builder, Indices[i],
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SubVecTy->getVectorNumElements(), 0))));
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return;
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}
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// Decompose the load instruction.
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LoadInst *LI = cast<LoadInst>(VecInst);
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Type *VecBasePtrTy = SubVecTy->getPointerTo(LI->getPointerAddressSpace());
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Value *VecBasePtr;
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unsigned int NumLoads = NumSubVectors;
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// In the case of stride 3 with a vector of 32 elements load the information
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// in the following way:
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// [0,1...,VF/2-1,VF/2+VF,VF/2+VF+1,...,2VF-1]
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if (DL.getTypeSizeInBits(VecTy) == 768) {
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Type *VecTran =
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VectorType::get(Type::getInt8Ty(LI->getContext()), 16)->getPointerTo();
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VecBasePtr = Builder.CreateBitCast(LI->getPointerOperand(), VecTran);
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NumLoads = NumSubVectors * 2;
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} else
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VecBasePtr = Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
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// Generate N loads of T type.
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for (unsigned i = 0; i < NumLoads; i++) {
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// TODO: Support inbounds GEP.
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Value *NewBasePtr = Builder.CreateGEP(VecBasePtr, Builder.getInt32(i));
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Instruction *NewLoad =
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Builder.CreateAlignedLoad(NewBasePtr, LI->getAlignment());
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DecomposedVectors.push_back(NewLoad);
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}
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}
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// Create shuffle mask for concatenation of two half vectors.
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// Low = false: mask generated for the shuffle
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// shuffle(VEC1,VEC2,{NumElement/2, NumElement/2+1, NumElement/2+2...,
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// NumElement-1, NumElement+NumElement/2,
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// NumElement+NumElement/2+1..., 2*NumElement-1})
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// = concat(high_half(VEC1),high_half(VEC2))
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// Low = true: mask generated for the shuffle
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// shuffle(VEC1,VEC2,{0,1,2,...,NumElement/2-1,NumElement,
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// NumElement+1...,NumElement+NumElement/2-1})
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// = concat(low_half(VEC1),low_half(VEC2))
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static void createConcatShuffleMask(int NumElements,
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SmallVectorImpl<uint32_t> &Mask, bool Low) {
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int NumHalfElements = NumElements / 2;
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int Offset = Low ? 0 : NumHalfElements;
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for (int i = 0; i < NumHalfElements; ++i)
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Mask.push_back(i + Offset);
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for (int i = 0; i < NumHalfElements; ++i)
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Mask.push_back(i + Offset + NumElements);
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}
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// Changing the scale of the vector type by reducing the number of elements and
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// doubling the scalar size.
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static MVT scaleVectorType(MVT VT) {
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unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2;
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return MVT::getVectorVT(MVT::getIntegerVT(ScalarSize),
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VT.getVectorNumElements() / 2);
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}
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void X86InterleavedAccessGroup::interleave8bitStride4(
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ArrayRef<Instruction *> Matrix, SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned numberOfElement) {
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// Example: Assuming we start from the following vectors:
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// Matrix[0]= c0 c1 c2 c3 c4 ... c31
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// Matrix[1]= m0 m1 m2 m3 m4 ... m31
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// Matrix[2]= y0 y1 y2 y3 y4 ... y31
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// Matrix[3]= k0 k1 k2 k3 k4 ... k31
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MVT VT = MVT::getVectorVT(MVT::i8, numberOfElement);
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MVT HalfVT = scaleVectorType(VT);
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TransposedMatrix.resize(4);
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SmallVector<uint32_t, 32> MaskHigh;
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SmallVector<uint32_t, 32> MaskLow;
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SmallVector<uint32_t, 32> MaskHighTemp1;
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SmallVector<uint32_t, 32> MaskLowTemp1;
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SmallVector<uint32_t, 32> MaskHighWord;
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SmallVector<uint32_t, 32> MaskLowWord;
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SmallVector<uint32_t, 32> ConcatLow;
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SmallVector<uint32_t, 32> ConcatHigh;
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// MaskHighTemp and MaskLowTemp built in the vpunpckhbw and vpunpcklbw X86
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// shuffle pattern.
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createUnpackShuffleMask<uint32_t>(VT, MaskHigh, false, false);
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createUnpackShuffleMask<uint32_t>(VT, MaskLow, true, false);
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// MaskHighTemp1 and MaskLowTemp1 built in the vpunpckhdw and vpunpckldw X86
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// shuffle pattern.
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createUnpackShuffleMask<uint32_t>(HalfVT, MaskLowTemp1, true, false);
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createUnpackShuffleMask<uint32_t>(HalfVT, MaskHighTemp1, false, false);
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scaleShuffleMask<uint32_t>(2, MaskHighTemp1, MaskHighWord);
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scaleShuffleMask<uint32_t>(2, MaskLowTemp1, MaskLowWord);
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// IntrVec1Low = c0 m0 c1 m1 ... c7 m7 | c16 m16 c17 m17 ... c23 m23
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// IntrVec1High = c8 m8 c9 m9 ... c15 m15 | c24 m24 c25 m25 ... c31 m31
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// IntrVec2Low = y0 k0 y1 k1 ... y7 k7 | y16 k16 y17 k17 ... y23 k23
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// IntrVec2High = y8 k8 y9 k9 ... y15 k15 | y24 k24 y25 k25 ... y31 k31
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Value *IntrVec1Low =
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Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow);
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Value *IntrVec1High =
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Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh);
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Value *IntrVec2Low =
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Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow);
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Value *IntrVec2High =
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Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh);
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// cmyk4 cmyk5 cmyk6 cmyk7 | cmyk20 cmyk21 cmyk22 cmyk23
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// cmyk12 cmyk13 cmyk14 cmyk15 | cmyk28 cmyk29 cmyk30 cmyk31
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// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk16 cmyk17 cmyk18 cmyk19
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// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk24 cmyk25 cmyk26 cmyk27
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Value *High =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskHighWord);
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Value *High1 =
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Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, MaskHighWord);
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Value *Low =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskLowWord);
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Value *Low1 =
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Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, MaskLowWord);
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if (VT == MVT::v16i8) {
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TransposedMatrix[0] = Low;
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TransposedMatrix[1] = High;
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TransposedMatrix[2] = Low1;
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TransposedMatrix[3] = High1;
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return;
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}
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// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk4 cmyk5 cmyk6 cmyk7
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// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk12 cmyk13 cmyk14 cmyk15
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// cmyk16 cmyk17 cmyk18 cmyk19 | cmyk20 cmyk21 cmyk22 cmyk23
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// cmyk24 cmyk25 cmyk26 cmyk27 | cmyk28 cmyk29 cmyk30 cmyk31
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// ConcatHigh and ConcatLow built in the vperm2i128 and vinserti128 X86
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// shuffle pattern.
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SmallVector<uint32_t, 32> ConcatHigh12, ConcatHigh13;
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createConcatShuffleMask(numberOfElement, ConcatLow, true);
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createConcatShuffleMask(numberOfElement, ConcatHigh, false);
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TransposedMatrix[0] = Builder.CreateShuffleVector(Low, High, ConcatLow);
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TransposedMatrix[1] = Builder.CreateShuffleVector(Low1, High1, ConcatLow);
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TransposedMatrix[2] = Builder.CreateShuffleVector(Low, High, ConcatHigh);
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TransposedMatrix[3] = Builder.CreateShuffleVector(Low1, High1, ConcatHigh);
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}
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// createShuffleStride returns shuffle mask of size N.
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// The shuffle pattern is as following :
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// {0, Stride%(VF/Lane), (2*Stride%(VF/Lane))...(VF*Stride/Lane)%(VF/Lane),
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// (VF/ Lane) ,(VF / Lane)+Stride%(VF/Lane),...,
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// (VF / Lane)+(VF*Stride/Lane)%(VF/Lane)}
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// Where Lane is the # of lanes in a register:
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// VectorSize = 128 => Lane = 1
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// VectorSize = 256 => Lane = 2
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// For example shuffle pattern for VF 16 register size 256 -> lanes = 2
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// {<[0|3|6|1|4|7|2|5]-[8|11|14|9|12|15|10|13]>}
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static void createShuffleStride(MVT VT, int Stride,
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SmallVectorImpl<uint32_t> &Mask) {
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int VectorSize = VT.getSizeInBits();
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int VF = VT.getVectorNumElements();
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int LaneCount = std::max(VectorSize / 128, 1);
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for (int Lane = 0; Lane < LaneCount; Lane++)
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for (int i = 0, LaneSize = VF / LaneCount; i != LaneSize; ++i)
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Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane);
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}
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// setGroupSize sets 'SizeInfo' to the size(number of elements) of group
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// inside mask a shuffleMask. A mask contains exactly 3 groups, where
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// each group is a monotonically increasing sequence with stride 3.
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// For example shuffleMask {0,3,6,1,4,7,2,5} => {3,3,2}
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static void setGroupSize(MVT VT, SmallVectorImpl<uint32_t> &SizeInfo) {
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int VectorSize = VT.getSizeInBits();
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int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1);
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for (int i = 0, FirstGroupElement = 0; i < 3; i++) {
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int GroupSize = std::ceil((VF - FirstGroupElement) / 3.0);
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SizeInfo.push_back(GroupSize);
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FirstGroupElement = ((GroupSize)*3 + FirstGroupElement) % VF;
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}
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}
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// DecodePALIGNRMask returns the shuffle mask of vpalign instruction.
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// vpalign works according to lanes
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// Where Lane is the # of lanes in a register:
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// VectorWide = 128 => Lane = 1
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// VectorWide = 256 => Lane = 2
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// For Lane = 1 shuffle pattern is: {DiffToJump,...,DiffToJump+VF-1}.
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// For Lane = 2 shuffle pattern is:
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// {DiffToJump,...,VF/2-1,VF,...,DiffToJump+VF-1}.
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// Imm variable sets the offset amount. The result of the
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// function is stored inside ShuffleMask vector and it built as described in
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// the begin of the description. AlignDirection is a boolean that indecat the
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// direction of the alignment. (false - align to the "right" side while true -
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// align to the "left" side)
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static void DecodePALIGNRMask(MVT VT, unsigned Imm,
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SmallVectorImpl<uint32_t> &ShuffleMask,
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bool AlignDirection = true, bool Unary = false) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1);
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unsigned NumLaneElts = NumElts / NumLanes;
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Imm = AlignDirection ? Imm : (NumLaneElts - Imm);
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unsigned Offset = Imm * (VT.getScalarSizeInBits() / 8);
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for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
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for (unsigned i = 0; i != NumLaneElts; ++i) {
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unsigned Base = i + Offset;
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// if i+offset is out of this lane then we actually need the other source
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// If Unary the other source is the first source.
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if (Base >= NumLaneElts)
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Base = Unary ? Base % NumLaneElts : Base + NumElts - NumLaneElts;
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ShuffleMask.push_back(Base + l);
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}
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}
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}
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void X86InterleavedAccessGroup::deinterleave8bitStride3(
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ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned VecElems) {
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// Example: Assuming we start from the following vectors:
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// Matrix[0]= a0 b0 c0 a1 b1 c1 a2 b2
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// Matrix[1]= c2 a3 b3 c3 a4 b4 c4 a5
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// Matrix[2]= b5 c5 a6 b6 c6 a7 b7 c7
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TransposedMatrix.resize(3);
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SmallVector<uint32_t, 32> Concat;
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SmallVector<uint32_t, 32> VPShuf;
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SmallVector<uint32_t, 32> VPAlign[2];
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SmallVector<uint32_t, 32> VPAlign2;
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SmallVector<uint32_t, 32> VPAlign3;
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SmallVector<uint32_t, 3> GroupSize;
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Value *Vec[3], *TempVector[3];
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MVT VT = MVT::getVT(Shuffles[0]->getType());
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for (unsigned i = 0; i < VecElems && VecElems == 32; ++i)
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Concat.push_back(i);
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createShuffleStride(VT, 3, VPShuf);
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setGroupSize(VT, GroupSize);
|
|
|
|
for (int i = 0; i < 2; i++)
|
|
DecodePALIGNRMask(VT, GroupSize[2 - i], VPAlign[i], false);
|
|
|
|
DecodePALIGNRMask(VT, GroupSize[2] + GroupSize[1], VPAlign2, true, true);
|
|
DecodePALIGNRMask(VT, GroupSize[1], VPAlign3, true, true);
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = VecElems == 32
|
|
? Builder.CreateShuffleVector(InVec[i], InVec[i + 3], Concat)
|
|
: InVec[i];
|
|
|
|
// Vec[0]= a0 a1 a2 b0 b1 b2 c0 c1
|
|
// Vec[1]= c2 c3 c4 a3 a4 a5 b3 b4
|
|
// Vec[2]= b5 b6 b7 c5 c6 c7 a6 a7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(
|
|
Vec[i], UndefValue::get(Vec[0]->getType()), VPShuf);
|
|
|
|
// TempVector[0]= a6 a7 a0 a1 a2 b0 b1 b2
|
|
// TempVector[1]= c0 c1 c2 c3 c4 a3 a4 a5
|
|
// TempVector[2]= b3 b4 b5 b6 b7 c5 c6 c7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
TempVector[i] =
|
|
Builder.CreateShuffleVector(Vec[(i + 2) % 3], Vec[i], VPAlign[0]);
|
|
|
|
// Vec[0]= a3 a4 a5 a6 a7 a0 a1 a2
|
|
// Vec[1]= c5 c6 c7 c0 c1 c2 c3 c4
|
|
// Vec[2]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(TempVector[(i + 1) % 3], TempVector[i],
|
|
VPAlign[1]);
|
|
|
|
// TransposedMatrix[0]= a0 a1 a2 a3 a4 a5 a6 a7
|
|
// TransposedMatrix[1]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
// TransposedMatrix[2]= c0 c1 c2 c3 c4 c5 c6 c7
|
|
|
|
Value *TempVec = Builder.CreateShuffleVector(
|
|
Vec[1], UndefValue::get(Vec[1]->getType()), VPAlign3);
|
|
TransposedMatrix[0] = Builder.CreateShuffleVector(
|
|
Vec[0], UndefValue::get(Vec[1]->getType()), VPAlign2);
|
|
TransposedMatrix[1] = VecElems == 8 ? Vec[2] : TempVec;
|
|
TransposedMatrix[2] = VecElems == 8 ? TempVec : Vec[2];
|
|
|
|
return;
|
|
}
|
|
|
|
void X86InterleavedAccessGroup::transpose_4x4(
|
|
ArrayRef<Instruction *> Matrix,
|
|
SmallVectorImpl<Value *> &TransposedMatrix) {
|
|
assert(Matrix.size() == 4 && "Invalid matrix size");
|
|
TransposedMatrix.resize(4);
|
|
|
|
// dst = src1[0,1],src2[0,1]
|
|
uint32_t IntMask1[] = {0, 1, 4, 5};
|
|
ArrayRef<uint32_t> Mask = makeArrayRef(IntMask1, 4);
|
|
Value *IntrVec1 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
|
|
Value *IntrVec2 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
|
|
|
|
// dst = src1[2,3],src2[2,3]
|
|
uint32_t IntMask2[] = {2, 3, 6, 7};
|
|
Mask = makeArrayRef(IntMask2, 4);
|
|
Value *IntrVec3 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
|
|
Value *IntrVec4 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
|
|
|
|
// dst = src1[0],src2[0],src1[2],src2[2]
|
|
uint32_t IntMask3[] = {0, 4, 2, 6};
|
|
Mask = makeArrayRef(IntMask3, 4);
|
|
TransposedMatrix[0] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
|
|
TransposedMatrix[2] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
|
|
|
|
// dst = src1[1],src2[1],src1[3],src2[3]
|
|
uint32_t IntMask4[] = {1, 5, 3, 7};
|
|
Mask = makeArrayRef(IntMask4, 4);
|
|
TransposedMatrix[1] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
|
|
TransposedMatrix[3] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
|
|
}
|
|
|
|
// Lowers this interleaved access group into X86-specific
|
|
// instructions/intrinsics.
|
|
bool X86InterleavedAccessGroup::lowerIntoOptimizedSequence() {
|
|
SmallVector<Instruction *, 4> DecomposedVectors;
|
|
SmallVector<Value *, 4> TransposedVectors;
|
|
VectorType *ShuffleTy = Shuffles[0]->getType();
|
|
|
|
if (isa<LoadInst>(Inst)) {
|
|
// Try to generate target-sized register(/instruction).
|
|
decompose(Inst, Factor, ShuffleTy, DecomposedVectors);
|
|
|
|
Type *ShuffleEltTy = Inst->getType();
|
|
unsigned NumSubVecElems = ShuffleEltTy->getVectorNumElements() / Factor;
|
|
// Perform matrix-transposition in order to compute interleaved
|
|
// results by generating some sort of (optimized) target-specific
|
|
// instructions.
|
|
|
|
switch (NumSubVecElems) {
|
|
default:
|
|
return false;
|
|
case 4:
|
|
transpose_4x4(DecomposedVectors, TransposedVectors);
|
|
break;
|
|
case 8:
|
|
case 16:
|
|
case 32:
|
|
deinterleave8bitStride3(DecomposedVectors, TransposedVectors,
|
|
NumSubVecElems);
|
|
break;
|
|
}
|
|
|
|
// Now replace the unoptimized-interleaved-vectors with the
|
|
// transposed-interleaved vectors.
|
|
for (unsigned i = 0, e = Shuffles.size(); i < e; ++i)
|
|
Shuffles[i]->replaceAllUsesWith(TransposedVectors[Indices[i]]);
|
|
|
|
return true;
|
|
}
|
|
|
|
Type *ShuffleEltTy = ShuffleTy->getVectorElementType();
|
|
unsigned NumSubVecElems = ShuffleTy->getVectorNumElements() / Factor;
|
|
|
|
// Lower the interleaved stores:
|
|
// 1. Decompose the interleaved wide shuffle into individual shuffle
|
|
// vectors.
|
|
decompose(Shuffles[0], Factor, VectorType::get(ShuffleEltTy, NumSubVecElems),
|
|
DecomposedVectors);
|
|
|
|
// 2. Transpose the interleaved-vectors into vectors of contiguous
|
|
// elements.
|
|
switch (NumSubVecElems) {
|
|
case 4:
|
|
transpose_4x4(DecomposedVectors, TransposedVectors);
|
|
break;
|
|
case 16:
|
|
case 32:
|
|
interleave8bitStride4(DecomposedVectors, TransposedVectors, NumSubVecElems);
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
// 3. Concatenate the contiguous-vectors back into a wide vector.
|
|
Value *WideVec = concatenateVectors(Builder, TransposedVectors);
|
|
|
|
// 4. Generate a store instruction for wide-vec.
|
|
StoreInst *SI = cast<StoreInst>(Inst);
|
|
Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(),
|
|
SI->getAlignment());
|
|
|
|
return true;
|
|
}
|
|
|
|
// Lower interleaved load(s) into target specific instructions/
|
|
// intrinsics. Lowering sequence varies depending on the vector-types, factor,
|
|
// number of shuffles and ISA.
|
|
// Currently, lowering is supported for 4x64 bits with Factor = 4 on AVX.
|
|
bool X86TargetLowering::lowerInterleavedLoad(
|
|
LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
|
|
ArrayRef<unsigned> Indices, unsigned Factor) const {
|
|
assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
|
|
"Invalid interleave factor");
|
|
assert(!Shuffles.empty() && "Empty shufflevector input");
|
|
assert(Shuffles.size() == Indices.size() &&
|
|
"Unmatched number of shufflevectors and indices");
|
|
|
|
// Create an interleaved access group.
|
|
IRBuilder<> Builder(LI);
|
|
X86InterleavedAccessGroup Grp(LI, Shuffles, Indices, Factor, Subtarget,
|
|
Builder);
|
|
|
|
return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
|
|
}
|
|
|
|
bool X86TargetLowering::lowerInterleavedStore(StoreInst *SI,
|
|
ShuffleVectorInst *SVI,
|
|
unsigned Factor) const {
|
|
assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
|
|
"Invalid interleave factor");
|
|
|
|
assert(SVI->getType()->getVectorNumElements() % Factor == 0 &&
|
|
"Invalid interleaved store");
|
|
|
|
// Holds the indices of SVI that correspond to the starting index of each
|
|
// interleaved shuffle.
|
|
SmallVector<unsigned, 4> Indices;
|
|
auto Mask = SVI->getShuffleMask();
|
|
for (unsigned i = 0; i < Factor; i++)
|
|
Indices.push_back(Mask[i]);
|
|
|
|
ArrayRef<ShuffleVectorInst *> Shuffles = makeArrayRef(SVI);
|
|
|
|
// Create an interleaved access group.
|
|
IRBuilder<> Builder(SI);
|
|
X86InterleavedAccessGroup Grp(SI, Shuffles, Indices, Factor, Subtarget,
|
|
Builder);
|
|
|
|
return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
|
|
}
|
|
|