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f41c3c9239
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306514 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.1 KiB
LLVM
69 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=neon | FileCheck %s
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define i32 @sext_inc(i1 zeroext %x) {
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; CHECK-LABEL: sext_inc:
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; CHECK: @ BB#0:
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; CHECK-NEXT: eor r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%ext = sext i1 %x to i32
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%add = add i32 %ext, 1
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ret i32 %add
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}
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define <4 x i32> @sext_inc_vec(<4 x i1> %x) {
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; CHECK-LABEL: sext_inc_vec:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov.i16 d16, #0x1
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; CHECK-NEXT: vmov d17, r0, r1
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; CHECK-NEXT: veor d16, d17, d16
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; CHECK-NEXT: vmov.i32 q9, #0x1
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; CHECK-NEXT: vmovl.u16 q8, d16
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; CHECK-NEXT: vand q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%ext = sext <4 x i1> %x to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmpgt_sext_inc_vec:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d17, r2, r3
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.s32 q8, q9, q8
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; CHECK-NEXT: vmov.i32 q9, #0x1
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; CHECK-NEXT: vand q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%cmp = icmp sgt <4 x i32> %x, %y
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%ext = sext <4 x i1> %cmp to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmpne_sext_inc_vec:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d17, r2, r3
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; CHECK-NEXT: mov r12, sp
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; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vceq.i32 q8, q8, q9
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; CHECK-NEXT: vmov.i32 q9, #0x1
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; CHECK-NEXT: vand q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%cmp = icmp ne <4 x i32> %x, %y
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%ext = sext <4 x i1> %cmp to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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