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ba3a480f3cd23de9ec00f147389163d92ebcd708
archived-llvm/test/MC/Disassembler
History
Andrew V. Tischenko 1f42b92202 'into' instruction should not be decoded as a valid instr in 64-bit mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313735 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20 08:17:17 +00:00
..
AArch64
[AArch64] v8.3-a complex number support
2017-08-31 09:27:04 +00:00
AMDGPU
[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
2017-08-16 15:16:32 +00:00
ARC
[ARC] Add ARC backend.
2017-08-24 15:40:33 +00:00
ARM
[ARM][AArch64] v8.3-A Javascript Conversion
2017-08-22 11:08:21 +00:00
Hexagon
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
Lanai
[lanai] Add Lanai backend.
2016-03-28 13:09:54 +00:00
Mips
[mips] Implement the 'dext' aliases and it's disassembly alias.
2017-09-14 17:27:53 +00:00
PowerPC
[Power9] Add missing Power9 instructions.
2017-09-19 15:22:36 +00:00
Sparc
This change adds co-processor condition branching and conditional traps to the Sparc back-end.
2016-03-09 18:20:21 +00:00
SystemZ
[SystemZ] Add support for IBM z14 processor (3/3)
2017-07-17 17:44:20 +00:00
X86
'into' instruction should not be decoded as a valid instr in 64-bit mode
2017-09-20 08:17:17 +00:00
XCore
Reduce verbiage of lit.local.cfg files
2014-06-09 22:42:55 +00:00
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