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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
9.0 KiB
C++
248 lines
9.0 KiB
C++
//===-- ARMBuildAttributes.h - ARM Build Attributes -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains enumerations and support routines for ARM build attributes
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// as defined in ARM ABI addenda document (ABI release 2.08).
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//
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// ELF for the ARM Architecture r2.09 - November 30, 2012
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//
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// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_ARMBUILDATTRIBUTES_H
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#define LLVM_SUPPORT_ARMBUILDATTRIBUTES_H
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namespace llvm {
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class StringRef;
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namespace ARMBuildAttrs {
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enum SpecialAttr {
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// This is for the .cpu asm attr. It translates into one or more
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// AttrType (below) entries in the .ARM.attributes section in the ELF.
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SEL_CPU
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};
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enum AttrType {
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// Rest correspond to ELF/.ARM.attributes
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File = 1,
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CPU_raw_name = 4,
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CPU_name = 5,
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CPU_arch = 6,
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CPU_arch_profile = 7,
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ARM_ISA_use = 8,
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THUMB_ISA_use = 9,
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FP_arch = 10,
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WMMX_arch = 11,
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Advanced_SIMD_arch = 12,
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PCS_config = 13,
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ABI_PCS_R9_use = 14,
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ABI_PCS_RW_data = 15,
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ABI_PCS_RO_data = 16,
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ABI_PCS_GOT_use = 17,
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ABI_PCS_wchar_t = 18,
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ABI_FP_rounding = 19,
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ABI_FP_denormal = 20,
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ABI_FP_exceptions = 21,
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ABI_FP_user_exceptions = 22,
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ABI_FP_number_model = 23,
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ABI_align_needed = 24,
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ABI_align_preserved = 25,
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ABI_enum_size = 26,
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ABI_HardFP_use = 27,
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ABI_VFP_args = 28,
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ABI_WMMX_args = 29,
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ABI_optimization_goals = 30,
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ABI_FP_optimization_goals = 31,
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compatibility = 32,
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CPU_unaligned_access = 34,
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FP_HP_extension = 36,
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ABI_FP_16bit_format = 38,
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MPextension_use = 42, // recoded from 70 (ABI r2.08)
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DIV_use = 44,
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DSP_extension = 46,
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also_compatible_with = 65,
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conformance = 67,
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Virtualization_use = 68,
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/// Legacy Tags
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Section = 2, // deprecated (ABI r2.09)
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Symbol = 3, // deprecated (ABI r2.09)
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ABI_align8_needed = 24, // renamed to ABI_align_needed (ABI r2.09)
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ABI_align8_preserved = 25, // renamed to ABI_align_preserved (ABI r2.09)
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nodefaults = 64, // deprecated (ABI r2.09)
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T2EE_use = 66, // deprecated (ABI r2.09)
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MPextension_use_old = 70 // recoded to MPextension_use (ABI r2.08)
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};
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StringRef AttrTypeAsString(unsigned Attr, bool HasTagPrefix = true);
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StringRef AttrTypeAsString(AttrType Attr, bool HasTagPrefix = true);
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int AttrTypeFromString(StringRef Tag);
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// Magic numbers for .ARM.attributes
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enum AttrMagic {
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Format_Version = 0x41
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};
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// Legal Values for CPU_arch, (=6), uleb128
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enum CPUArch {
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Pre_v4 = 0,
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v4 = 1, // e.g. SA110
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v4T = 2, // e.g. ARM7TDMI
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v5T = 3, // e.g. ARM9TDMI
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v5TE = 4, // e.g. ARM946E_S
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v5TEJ = 5, // e.g. ARM926EJ_S
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v6 = 6, // e.g. ARM1136J_S
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v6KZ = 7, // e.g. ARM1176JZ_S
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v6T2 = 8, // e.g. ARM1156T2_S
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v6K = 9, // e.g. ARM1176JZ_S
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v7 = 10, // e.g. Cortex A8, Cortex M3
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v6_M = 11, // e.g. Cortex M1
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v6S_M = 12, // v6_M with the System extensions
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v7E_M = 13, // v7_M with DSP extensions
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v8_A = 14, // v8_A AArch32
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v8_R = 15, // e.g. Cortex R52
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v8_M_Base= 16, // v8_M_Base AArch32
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v8_M_Main= 17, // v8_M_Main AArch32
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};
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enum CPUArchProfile { // (=7), uleb128
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Not_Applicable = 0, // pre v7, or cross-profile code
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ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8)
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RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4)
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MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3)
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SystemProfile = (0x53) // 'S' Application or real-time profile
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};
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// The following have a lot of common use cases
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enum {
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Not_Allowed = 0,
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Allowed = 1,
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// Tag_ARM_ISA_use (=8), uleb128
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// Tag_THUMB_ISA_use, (=9), uleb128
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AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions)
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AllowThumbDerived = 3, // Thumb allowed, derived from arch/profile
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// Tag_FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10)
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AllowFPv2 = 2, // v2 FP ISA permitted (implies use of the v1 FP ISA)
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AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA)
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AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31
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AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA)
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AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31
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AllowFPARMv8A = 7, // Use of the ARM v8-A FP ISA was permitted
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AllowFPARMv8B = 8, // Use of the ARM v8-A FP ISA was permitted, but only
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// D0-D15, S0-S31
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// Tag_WMMX_arch, (=11), uleb128
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AllowWMMXv1 = 1, // The user permitted this entity to use WMMX v1
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AllowWMMXv2 = 2, // The user permitted this entity to use WMMX v2
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// Tag_Advanced_SIMD_arch, (=12), uleb128
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AllowNeon = 1, // SIMDv1 was permitted
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AllowNeon2 = 2, // SIMDv2 was permitted (Half-precision FP, MAC operations)
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AllowNeonARMv8 = 3, // ARM v8-A SIMD was permitted
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AllowNeonARMv8_1a = 4,// ARM v8.1-A SIMD was permitted (RDMA)
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// Tag_ABI_PCS_R9_use, (=14), uleb128
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R9IsGPR = 0, // R9 used as v6 (just another callee-saved register)
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R9IsSB = 1, // R9 used as a global static base rgister
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R9IsTLSPointer = 2, // R9 used as a thread local storage pointer
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R9Reserved = 3, // R9 not used by code associated with attributed entity
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// Tag_ABI_PCS_RW_data, (=15), uleb128
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AddressRWPCRel = 1, // Address RW static data PC-relative
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AddressRWSBRel = 2, // Address RW static data SB-relative
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AddressRWNone = 3, // No RW static data permitted
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// Tag_ABI_PCS_RO_data, (=14), uleb128
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AddressROPCRel = 1, // Address RO static data PC-relative
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AddressRONone = 2, // No RO static data permitted
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// Tag_ABI_PCS_GOT_use, (=17), uleb128
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AddressDirect = 1, // Address imported data directly
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AddressGOT = 2, // Address imported data indirectly (via GOT)
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// Tag_ABI_PCS_wchar_t, (=18), uleb128
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WCharProhibited = 0, // wchar_t is not used
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WCharWidth2Bytes = 2, // sizeof(wchar_t) == 2
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WCharWidth4Bytes = 4, // sizeof(wchar_t) == 4
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// Tag_ABI_align_needed, (=24), uleb128
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Align8Byte = 1,
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Align4Byte = 2,
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AlignReserved = 3,
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// Tag_ABI_align_needed, (=25), uleb128
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AlignNotPreserved = 0,
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AlignPreserve8Byte = 1,
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AlignPreserveAll = 2,
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// Tag_ABI_FP_denormal, (=20), uleb128
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PositiveZero = 0,
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IEEEDenormals = 1,
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PreserveFPSign = 2, // sign when flushed-to-zero is preserved
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// Tag_ABI_FP_number_model, (=23), uleb128
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AllowIEEENormal = 1,
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AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI])
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AllowIEEE754 = 3, // this code to use all the IEEE 754-defined FP encodings
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// Tag_ABI_enum_size, (=26), uleb128
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EnumProhibited = 0, // The user prohibited the use of enums when building
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// this entity.
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EnumSmallest = 1, // Enum is smallest container big enough to hold all
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// values.
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Enum32Bit = 2, // Enum is at least 32 bits.
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Enum32BitABI = 3, // Every enumeration visible across an ABI-complying
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// interface contains a value needing 32 bits to encode
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// it; other enums can be containerized.
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// Tag_ABI_HardFP_use, (=27), uleb128
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HardFPImplied = 0, // FP use should be implied by Tag_FP_arch
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HardFPSinglePrecision = 1, // Single-precision only
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// Tag_ABI_VFP_args, (=28), uleb128
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BaseAAPCS = 0,
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HardFPAAPCS = 1,
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ToolChainFPPCS = 2,
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CompatibleFPAAPCS = 3,
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// Tag_FP_HP_extension, (=36), uleb128
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AllowHPFP = 1, // Allow use of Half Precision FP
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// Tag_FP_16bit_format, (=38), uleb128
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FP16FormatIEEE = 1,
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FP16VFP3 = 2,
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// Tag_MPextension_use, (=42), uleb128
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AllowMP = 1, // Allow use of MP extensions
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// Tag_DIV_use, (=44), uleb128
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// Note: AllowDIVExt must be emitted if and only if the permission to use
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// hardware divide cannot be conveyed using AllowDIVIfExists or DisallowDIV
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AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no
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// info exists.
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DisallowDIV = 1, // Hardware divide explicitly disallowed.
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AllowDIVExt = 2, // Allow hardware divide as optional architecture
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// extension above the base arch specified by
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// Tag_CPU_arch and Tag_CPU_arch_profile.
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// Tag_Virtualization_use, (=68), uleb128
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AllowTZ = 1,
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AllowVirtualization = 2,
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AllowTZVirtualization = 3
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};
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} // namespace ARMBuildAttrs
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} // namespace llvm
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#endif
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