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beaee00a16da5bf52844f8cfdaa734cbdd919ba1
archived-llvm/test/CodeGen/MIR/AMDGPU
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Matt Arsenault d833ca999e AMDGPU: Don't use the default cpu in a few tests 
Avoids unnecessary test changes in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357539 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-03 00:00:58 +00:00
..
expected-target-index-name.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
intrinsics.mir
[GISel]: Verify COPIES involving generic registers.
2018-02-09 01:27:23 +00:00
invalid-target-index-operand.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
lit.local.cfg
…
machine-function-info-no-ir.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
machine-function-info-register-parse-error1.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
machine-function-info-register-parse-error2.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
machine-function-info.ll
AMDGPU: Don't use the default cpu in a few tests
2019-04-03 00:00:58 +00:00
mfi-frame-offset-reg-class.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-parse-error-frame-offset-reg.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-parse-error-scratch-rsrc-reg.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-parse-error-scratch-wave-offset-reg.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-parse-error-stack-ptr-offset-reg.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-scratch-rsrc-reg-reg-class.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-scratch-wave-offset-reg-class.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mfi-stack-ptr-offset-reg-class.mir
MIR: Allow targets to serialize MachineFunctionInfo
2019-03-14 22:54:43 +00:00
mir-canon-multi.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
parse-order-reserved-regs.mir
MIR: Freeze reserved regs after parsing everything
2019-03-27 16:12:26 +00:00
stack-id.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
syncscopes.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
target-flags.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
target-index-operands.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00