Files
archived-llvm/test/CodeGen/X86/vec_insert-7.ll
Craig Topper b6ab93e6a5 [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality

Differential Revision: https://reviews.llvm.org/D58884

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355324 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-04 19:12:16 +00:00

29 lines
1.0 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64
; MMX insertelement is not available; these are promoted to xmm.
; (Without SSE they are split to two ints, and the code is much better.)
define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
; X32-LABEL: mmx_movzl:
; X32: ## %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: movl $32, %eax
; X32-NEXT: movd %eax, %xmm0
; X32-NEXT: movdq2q %xmm0, %mm0
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
;
; X64-LABEL: mmx_movzl:
; X64: ## %bb.0:
; X64-NEXT: movl $32, %eax
; X64-NEXT: movq %rax, %xmm0
; X64-NEXT: retq
%tmp = bitcast x86_mmx %x to <2 x i32>
%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0
%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1
%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
ret x86_mmx %tmp9
}