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ca7fd00a1151bc551cf33efe5c4c8787d3f75cd3
archived-llvm/test/CodeGen/MIR/AMDGPU
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Puyan Lotfi a7f9b6aaad [MIR-Canon] Improving performance by switching to named vregs.
No more skipping thounsands of vregs. Much faster running time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329246 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 00:27:15 +00:00
..
expected-target-index-name.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
intrinsics.mir
[GISel]: Verify COPIES involving generic registers.
2018-02-09 01:27:23 +00:00
invalid-target-index-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lit.local.cfg
…
mir-canon-multi.mir
[MIR-Canon] Improving performance by switching to named vregs.
2018-04-05 00:27:15 +00:00
stack-id.mir
Add an ID field to StackObjects
2017-07-20 21:03:45 +00:00
syncscopes.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
target-flags.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
target-index-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
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