Simon Pilgrim cbe9dfdbe8 [AMDGPU] Regenerate bswap/bitreverse tests. ...

Make codegen changes more obvious in D58017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354863 91177308-0d34-0410-b5e6-96231b3b80d8

2019-02-26 11:01:08 +00:00

..

AArch64

[AArch64] Add support for Cortex-A76 and Cortex-A76AE

2019-02-25 15:08:27 +00:00

AMDGPU

[AMDGPU] Regenerate bswap/bitreverse tests.

2019-02-26 11:01:08 +00:00

ARC

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ARM

[ARM] Add some more missing T1 opcodes for the peephole optimisier

2019-02-25 15:50:54 +00:00

AVR

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BPF

[BPF] make test case reloc-btf.ll tolerable for old compilers

2019-02-20 00:22:19 +00:00

Generic

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Hexagon

[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap

2019-02-21 19:42:39 +00:00

Inputs

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Lanai

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Mips

[Mips] Fix missing masking in fast-isel of br (PR40325)

2019-02-25 18:54:17 +00:00

MIR

[X86] Add FPCW as an implicit use on floating point load instructions.

2019-02-08 20:50:09 +00:00

MSP430

Enable integrated assembler on MSP430 by default.

2019-02-05 18:01:45 +00:00

NVPTX

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PowerPC

Fixed typos in tests: s/CHEKC/CHECK/

2019-02-25 13:41:59 +00:00

RISCV

[RISCV] Re-organise calling convention tests

2019-02-19 13:47:19 +00:00

SPARC

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SystemZ

Recommit "[SystemZ] Do not emit VEXTEND or VROUND nodes without vector support."

2019-02-15 19:13:55 +00:00

Thumb

[ARM] Add some more missing T1 opcodes for the peephole optimisier

2019-02-25 15:50:54 +00:00

Thumb2

[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

2019-02-22 12:23:31 +00:00

WebAssembly

[WebAssembly] Properly align fp128 arguments in outgoing varargs arguments

2019-02-26 05:20:19 +00:00

WinCFGuard

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WinEH

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X86

[X86] Fix bug in x86_intrcc with arg copy elision

2019-02-26 02:11:25 +00:00

XCore

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