Simon Pilgrim cc6487ed56 [X86][SSE] Disable shouldFoldConstantShiftPairToMask for btver1/btver2 targets (PR40758) ...

As detailed on PR40758, Bobcat/Jaguar can perform vector immediate shifts on the same pipes as vector ANDs with the same latency - so it doesn't make sense to replace a shl+lshr with a shift+and pair as it requires an additional mask (with the extra constant pool, loading and register pressure costs).

Differential Revision: https://reviews.llvm.org/D61068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359293 91177308-0d34-0410-b5e6-96231b3b80d8

2019-04-26 10:49:13 +00:00

..

AArch64

Fix alignment in AArch64InstructionSelector::emitConstantPoolEntry()

2019-04-26 08:31:00 +00:00

AMDGPU

[AMDGPU] Add gfx1010 target definitions

2019-04-24 17:03:15 +00:00

ARC

[ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores.

2019-03-20 20:06:21 +00:00

ARM

[ARM][FIX] Add missing f16.lane.vldN/vstN lowering

2019-04-23 09:36:39 +00:00

AVR

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00

BPF

[BPF] add proper multi-dimensional array support

2019-03-28 21:59:49 +00:00

Generic

Fix nondeterminism introduced in r353954

2019-03-26 12:18:08 +00:00

Hexagon

Enable LoopVectorization by default.

2019-04-25 04:49:48 +00:00

Inputs

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Lanai

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Mips

[MIPS] Use custom bitcast lowering to avoid excessive instructions

2019-04-25 07:47:28 +00:00

MIR

[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

2019-04-05 19:28:09 +00:00

MSP430

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00

NVPTX

PTX 6.3 extends wmma instruction to support s8/u8/s4/u4/b1 -> s32.

2019-04-25 22:27:57 +00:00

PowerPC

[PowerPC] Allow using initial-exec TLS with PIC

2019-04-24 22:12:22 +00:00

RISCV

[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS

2019-04-16 14:38:32 +00:00

SPARC

[SPARC] Use the correct register set for the "r" asm constraint.

2019-04-23 15:15:33 +00:00

SystemZ

Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg

2019-04-10 18:00:41 +00:00

Thumb

[ARM] Add an extra constant hoisting test. NFC

2019-04-10 18:05:57 +00:00

Thumb2

[ARM] Update check for CBZ in Ifcvt

2019-04-23 12:11:26 +00:00

WebAssembly

[WebAssembly] Emit br_table for most switch instructions

2019-04-23 21:30:30 +00:00

WinCFGuard

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WinEH

Fix invalid target triples in tests. (NFC)

2019-03-04 23:37:41 +00:00

X86

[X86][SSE] Disable shouldFoldConstantShiftPairToMask for btver1/btver2 targets (PR40758)

2019-04-26 10:49:13 +00:00

XCore

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00