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c8116a946b
Implement aggregate structure split to simpler types in splitToValueTypes. splitToValueTypes is used for return values. According to MipsABIInfo from clang/lib/CodeGen/TargetInfo.cpp, aggregate structure arguments for O32 always get simplified and thus will remain unsupported by the MIPS GlobalISel for the time being. For O32, aggregate structures can be encountered only for complex number returns e.g. 'complex float' or 'complex double' from <complex.h>. Differential Revision: https://reviews.llvm.org/D67963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372957 91177308-0d34-0410-b5e6-96231b3b80d8
721 lines
25 KiB
C++
721 lines
25 KiB
C++
//===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsCallLowering.h"
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#include "MipsCCState.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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using namespace llvm;
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MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
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: CallLowering(&TLI) {}
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bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
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const EVT &VT) {
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if (VA.isRegLoc()) {
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assignValueToReg(VReg, VA, VT);
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} else if (VA.isMemLoc()) {
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assignValueToAddress(VReg, VA);
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} else {
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return false;
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}
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return true;
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}
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bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex,
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const EVT &VT) {
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for (unsigned i = 0; i < VRegs.size(); ++i)
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if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
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return false;
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return true;
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}
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void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
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SmallVectorImpl<Register> &VRegs) {
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if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
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std::reverse(VRegs.begin(), VRegs.end());
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}
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bool MipsCallLowering::MipsHandler::handle(
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ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) {
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SmallVector<Register, 4> VRegs;
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unsigned SplitLength;
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const Function &F = MIRBuilder.getMF().getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
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MIRBuilder.getMF().getSubtarget().getTargetLowering());
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for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
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++ArgsIndex, ArgLocsIndex += SplitLength) {
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EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
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SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
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F.getCallingConv(), VT);
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assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
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if (SplitLength > 1) {
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VRegs.clear();
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MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
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F.getContext(), F.getCallingConv(), VT);
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for (unsigned i = 0; i < SplitLength; ++i)
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VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
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if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
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VT))
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return false;
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} else {
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if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
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return false;
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}
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}
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return true;
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}
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namespace {
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class IncomingValueHandler : public MipsCallLowering::MipsHandler {
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public:
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IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
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: MipsHandler(MIRBuilder, MRI) {}
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private:
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void assignValueToReg(Register ValVReg, const CCValAssign &VA,
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const EVT &VT) override;
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Register getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
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bool handleSplit(SmallVectorImpl<Register> &VRegs,
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ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
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Register ArgsReg, const EVT &VT) override;
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virtual void markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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void buildLoad(Register Val, const CCValAssign &VA) {
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MachineMemOperand *MMO;
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Register Addr = getStackAddress(VA, MMO);
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MIRBuilder.buildLoad(Val, Addr, *MMO);
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}
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};
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class CallReturnHandler : public IncomingValueHandler {
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public:
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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void markPhysRegUsed(unsigned PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void IncomingValueHandler::assignValueToReg(Register ValVReg,
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const CCValAssign &VA,
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const EVT &VT) {
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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Register PhysReg = VA.getLocReg();
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if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
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: Mips::BuildPairF64)
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.addDef(ValVReg)
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.addUse(PhysReg + (STI.isLittle() ? 0 : 1))
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.addUse(PhysReg + (STI.isLittle() ? 1 : 0))
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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markPhysRegUsed(PhysReg);
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markPhysRegUsed(PhysReg + 1);
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} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder.buildInstr(Mips::MTC1)
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.addDef(ValVReg)
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.addUse(PhysReg)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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markPhysRegUsed(PhysReg);
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} else {
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switch (VA.getLocInfo()) {
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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}
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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}
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markPhysRegUsed(PhysReg);
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}
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}
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Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) {
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MachineFunction &MF = MIRBuilder.getMF();
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unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
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unsigned Offset = VA.getLocMemOffset();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MachinePointerInfo MPO =
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MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
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unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
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MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
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Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
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MIRBuilder.buildFrameIndex(AddrReg, FI);
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return AddrReg;
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}
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void IncomingValueHandler::assignValueToAddress(Register ValVReg,
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const CCValAssign &VA) {
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if (VA.getLocInfo() == CCValAssign::SExt ||
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VA.getLocInfo() == CCValAssign::ZExt ||
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VA.getLocInfo() == CCValAssign::AExt) {
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Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
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buildLoad(LoadReg, VA);
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MIRBuilder.buildTrunc(ValVReg, LoadReg);
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} else
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buildLoad(ValVReg, VA);
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}
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bool IncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex,
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Register ArgsReg, const EVT &VT) {
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
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return false;
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setLeastSignificantFirst(VRegs);
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MIRBuilder.buildMerge(ArgsReg, VRegs);
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return true;
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}
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namespace {
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class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
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public:
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OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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void assignValueToReg(Register ValVReg, const CCValAssign &VA,
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const EVT &VT) override;
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Register getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
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bool handleSplit(SmallVectorImpl<Register> &VRegs,
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ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
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Register ArgsReg, const EVT &VT) override;
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Register extendRegister(Register ValReg, const CCValAssign &VA);
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void OutgoingValueHandler::assignValueToReg(Register ValVReg,
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const CCValAssign &VA,
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const EVT &VT) {
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Register PhysReg = VA.getLocReg();
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
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: Mips::ExtractElementF64)
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.addDef(PhysReg + (STI.isLittle() ? 1 : 0))
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.addUse(ValVReg)
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.addImm(1)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
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: Mips::ExtractElementF64)
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.addDef(PhysReg + (STI.isLittle() ? 0 : 1))
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.addUse(ValVReg)
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.addImm(0)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder.buildInstr(Mips::MFC1)
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.addDef(PhysReg)
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.addUse(ValVReg)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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} else {
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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}
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Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) {
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MachineFunction &MF = MIRBuilder.getMF();
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const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
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LLT p0 = LLT::pointer(0, 32);
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LLT s32 = LLT::scalar(32);
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Register SPReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
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Register OffsetReg = MRI.createGenericVirtualRegister(s32);
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unsigned Offset = VA.getLocMemOffset();
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MIRBuilder.buildConstant(OffsetReg, Offset);
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Register AddrReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
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MachinePointerInfo MPO =
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MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
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unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
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unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
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MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align);
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return AddrReg;
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}
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void OutgoingValueHandler::assignValueToAddress(Register ValVReg,
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const CCValAssign &VA) {
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MachineMemOperand *MMO;
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Register Addr = getStackAddress(VA, MMO);
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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}
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Register OutgoingValueHandler::extendRegister(Register ValReg,
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const CCValAssign &VA) {
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LLT LocTy{VA.getLocVT()};
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt: {
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Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildSExt(ExtReg, ValReg);
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return ExtReg;
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}
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case CCValAssign::ZExt: {
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Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildZExt(ExtReg, ValReg);
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return ExtReg;
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}
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case CCValAssign::AExt: {
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Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildAnyExt(ExtReg, ValReg);
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return ExtReg;
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}
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// TODO : handle upper extends
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case CCValAssign::Full:
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return ValReg;
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default:
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break;
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}
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llvm_unreachable("unable to extend register");
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}
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bool OutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex,
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Register ArgsReg, const EVT &VT) {
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MIRBuilder.buildUnmerge(VRegs, ArgsReg);
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setLeastSignificantFirst(VRegs);
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
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return false;
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return true;
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}
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static bool isSupportedArgumentType(Type *T) {
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if (T->isIntegerTy())
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isFloatingPointTy())
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return true;
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return false;
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}
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static bool isSupportedReturnType(Type *T) {
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if (T->isIntegerTy())
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isFloatingPointTy())
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return true;
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if (T->isAggregateType())
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return true;
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return false;
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}
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static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
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const ISD::ArgFlagsTy &Flags) {
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// > does not mean loss of information as type RegisterVT can't hold type VT,
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// it means that type VT is split into multiple registers of type RegisterVT
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if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
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return CCValAssign::LocInfo::Full;
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if (Flags.isSExt())
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return CCValAssign::LocInfo::SExt;
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if (Flags.isZExt())
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return CCValAssign::LocInfo::ZExt;
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return CCValAssign::LocInfo::AExt;
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}
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template <typename T>
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static void setLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
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const SmallVectorImpl<T> &Arguments) {
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for (unsigned i = 0; i < ArgLocs.size(); ++i) {
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const CCValAssign &VA = ArgLocs[i];
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CCValAssign::LocInfo LocInfo = determineLocInfo(
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Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
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if (VA.isMemLoc())
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ArgLocs[i] =
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CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
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VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
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else
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ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
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VA.getLocReg(), VA.getLocVT(), LocInfo);
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}
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}
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bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val,
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ArrayRef<Register> VRegs) const {
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MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
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if (Val != nullptr && !isSupportedReturnType(Val->getType()))
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return false;
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if (!VRegs.empty()) {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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SmallVector<ArgInfo, 8> RetInfos;
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SmallVector<unsigned, 8> OrigArgIndices;
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ArgInfo ArgRetInfo(VRegs, Val->getType());
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setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
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splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices);
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SmallVector<ISD::OutputArg, 8> Outs;
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subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
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setLocInfo(ArgLocs, Outs);
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OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
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if (!RetHandler.handle(ArgLocs, RetInfos)) {
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return false;
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}
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}
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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bool MipsCallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs) const {
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// Quick exit if there aren't any args.
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if (F.arg_empty())
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return true;
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for (auto &Arg : F.args()) {
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if (!isSupportedArgumentType(Arg.getType()))
|
|
return false;
|
|
}
|
|
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const DataLayout &DL = MF.getDataLayout();
|
|
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
|
|
|
|
SmallVector<ArgInfo, 8> ArgInfos;
|
|
SmallVector<unsigned, 8> OrigArgIndices;
|
|
unsigned i = 0;
|
|
for (auto &Arg : F.args()) {
|
|
ArgInfo AInfo(VRegs[i], Arg.getType());
|
|
setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
|
|
ArgInfos.push_back(AInfo);
|
|
OrigArgIndices.push_back(i);
|
|
++i;
|
|
}
|
|
|
|
SmallVector<ISD::InputArg, 8> Ins;
|
|
subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
const MipsTargetMachine &TM =
|
|
static_cast<const MipsTargetMachine &>(MF.getTarget());
|
|
const MipsABIInfo &ABI = TM.getABI();
|
|
CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
|
|
1);
|
|
CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
|
|
setLocInfo(ArgLocs, Ins);
|
|
|
|
IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
|
|
if (!Handler.handle(ArgLocs, ArgInfos))
|
|
return false;
|
|
|
|
if (F.isVarArg()) {
|
|
ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
|
|
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
|
|
|
|
int VaArgOffset;
|
|
unsigned RegSize = 4;
|
|
if (ArgRegs.size() == Idx)
|
|
VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
|
|
else {
|
|
VaArgOffset =
|
|
(int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
|
|
(int)(RegSize * (ArgRegs.size() - Idx));
|
|
}
|
|
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
|
|
MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
|
|
|
|
for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
|
|
MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
|
|
|
|
MachineInstrBuilder Copy =
|
|
MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
|
|
FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
|
|
MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
|
|
MachineInstrBuilder FrameIndex =
|
|
MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
|
|
MachineMemOperand *MMO =
|
|
MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize,
|
|
/* Alignment */ RegSize);
|
|
MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
|
|
CallLoweringInfo &Info) const {
|
|
|
|
if (Info.CallConv != CallingConv::C)
|
|
return false;
|
|
|
|
for (auto &Arg : Info.OrigArgs) {
|
|
if (!isSupportedArgumentType(Arg.Ty))
|
|
return false;
|
|
if (Arg.Flags[0].isByVal())
|
|
return false;
|
|
if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
|
|
return false;
|
|
}
|
|
|
|
if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
|
|
return false;
|
|
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const Function &F = MF.getFunction();
|
|
const DataLayout &DL = MF.getDataLayout();
|
|
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
|
|
const MipsTargetMachine &TM =
|
|
static_cast<const MipsTargetMachine &>(MF.getTarget());
|
|
const MipsABIInfo &ABI = TM.getABI();
|
|
|
|
MachineInstrBuilder CallSeqStart =
|
|
MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
|
|
|
|
const bool IsCalleeGlobalPIC =
|
|
Info.Callee.isGlobal() && TM.isPositionIndependent();
|
|
|
|
MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
|
|
Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
|
|
MIB.addDef(Mips::SP, RegState::Implicit);
|
|
if (IsCalleeGlobalPIC) {
|
|
Register CalleeReg =
|
|
MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
|
|
MachineInstr *CalleeGlobalValue =
|
|
MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
|
|
if (!Info.Callee.getGlobal()->hasLocalLinkage())
|
|
CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
|
|
MIB.addUse(CalleeReg);
|
|
} else
|
|
MIB.add(Info.Callee);
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
|
|
|
|
TargetLowering::ArgListTy FuncOrigArgs;
|
|
FuncOrigArgs.reserve(Info.OrigArgs.size());
|
|
|
|
SmallVector<ArgInfo, 8> ArgInfos;
|
|
SmallVector<unsigned, 8> OrigArgIndices;
|
|
unsigned i = 0;
|
|
for (auto &Arg : Info.OrigArgs) {
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
Entry.Ty = Arg.Ty;
|
|
FuncOrigArgs.push_back(Entry);
|
|
|
|
ArgInfos.push_back(Arg);
|
|
OrigArgIndices.push_back(i);
|
|
++i;
|
|
}
|
|
|
|
SmallVector<ISD::OutputArg, 8> Outs;
|
|
subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
|
|
|
|
SmallVector<CCValAssign, 8> ArgLocs;
|
|
bool IsCalleeVarArg = false;
|
|
if (Info.Callee.isGlobal()) {
|
|
const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
|
|
IsCalleeVarArg = CF->isVarArg();
|
|
}
|
|
MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), 1);
|
|
const char *Call =
|
|
Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
|
|
CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
|
|
setLocInfo(ArgLocs, Outs);
|
|
|
|
OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
|
|
if (!RetHandler.handle(ArgLocs, ArgInfos)) {
|
|
return false;
|
|
}
|
|
|
|
unsigned NextStackOffset = CCInfo.getNextStackOffset();
|
|
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
|
|
unsigned StackAlignment = TFL->getStackAlignment();
|
|
NextStackOffset = alignTo(NextStackOffset, StackAlignment);
|
|
CallSeqStart.addImm(NextStackOffset).addImm(0);
|
|
|
|
if (IsCalleeGlobalPIC) {
|
|
MIRBuilder.buildCopy(
|
|
Register(Mips::GP),
|
|
MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel());
|
|
MIB.addDef(Mips::GP, RegState::Implicit);
|
|
}
|
|
MIRBuilder.insertInstr(MIB);
|
|
if (MIB->getOpcode() == Mips::JALRPseudo) {
|
|
const MipsSubtarget &STI =
|
|
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
|
|
MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
|
|
*STI.getRegBankInfo());
|
|
}
|
|
|
|
if (!Info.OrigRet.Ty->isVoidTy()) {
|
|
ArgInfos.clear();
|
|
SmallVector<unsigned, 8> OrigRetIndices;
|
|
|
|
splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices);
|
|
|
|
SmallVector<ISD::InputArg, 8> Ins;
|
|
subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
|
|
|
|
SmallVector<CCValAssign, 8> ArgLocs;
|
|
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call);
|
|
setLocInfo(ArgLocs, Ins);
|
|
|
|
CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
|
|
if (!Handler.handle(ArgLocs, ArgInfos))
|
|
return false;
|
|
}
|
|
|
|
MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
|
|
|
|
return true;
|
|
}
|
|
|
|
template <typename T>
|
|
void MipsCallLowering::subTargetRegTypeForCallingConv(
|
|
const Function &F, ArrayRef<ArgInfo> Args,
|
|
ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
|
|
const DataLayout &DL = F.getParent()->getDataLayout();
|
|
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
|
|
|
|
unsigned ArgNo = 0;
|
|
for (auto &Arg : Args) {
|
|
|
|
EVT VT = TLI.getValueType(DL, Arg.Ty);
|
|
MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
|
|
F.getCallingConv(), VT);
|
|
unsigned NumRegs = TLI.getNumRegistersForCallingConv(
|
|
F.getContext(), F.getCallingConv(), VT);
|
|
|
|
for (unsigned i = 0; i < NumRegs; ++i) {
|
|
ISD::ArgFlagsTy Flags = Arg.Flags[0];
|
|
|
|
if (i == 0)
|
|
Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL));
|
|
else
|
|
Flags.setOrigAlign(1);
|
|
|
|
ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
|
|
0);
|
|
}
|
|
++ArgNo;
|
|
}
|
|
}
|
|
|
|
void MipsCallLowering::splitToValueTypes(
|
|
const DataLayout &DL, const ArgInfo &OrigArg, unsigned OriginalIndex,
|
|
SmallVectorImpl<ArgInfo> &SplitArgs,
|
|
SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
|
|
|
|
SmallVector<EVT, 4> SplitEVTs;
|
|
SmallVector<Register, 4> SplitVRegs;
|
|
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
|
|
LLVMContext &Ctx = OrigArg.Ty->getContext();
|
|
|
|
ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitEVTs);
|
|
|
|
for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
|
|
ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
|
|
Info.Flags = OrigArg.Flags;
|
|
SplitArgs.push_back(Info);
|
|
SplitArgsOrigIndices.push_back(OriginalIndex);
|
|
}
|
|
}
|