Files
archived-llvm/test/CodeGen/ARM
Javed Absar 172d6c078b [ARM]: Assign cost of scaling used in addressing mode for ARM cores
This patch assigns cost of the scaling used in addressing.
On many ARM cores, a negated register offset takes longer than a
non-negated register offset, in a register-offset addressing mode.

For instance:

LDR R0, [R1, R2 LSL #2]
LDR R0, [R1, -R2 LSL #2]

Above, (1) takes less cycles than (2).

By assigning appropriate scaling factor cost, we enable the LLVM
to make the right trade-offs in the optimization and code-selection phase.

Differential Revision: http://reviews.llvm.org/D24857

Reviewers: jmolloy, rengolin




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284127 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-13 14:57:43 +00:00
..
2016-10-13 00:55:24 +00:00
2016-01-26 00:03:25 +00:00
2014-04-03 17:35:22 +00:00
2016-06-16 16:09:53 +00:00
2016-01-28 18:59:04 +00:00
2016-05-19 12:59:17 +00:00
2016-05-19 12:59:17 +00:00
2012-06-11 08:07:26 +00:00
2014-02-16 07:31:05 +00:00
2014-08-26 12:47:26 +00:00
2014-01-29 11:50:56 +00:00
2014-01-29 11:50:56 +00:00
2016-06-16 16:09:53 +00:00
2015-10-26 20:49:49 +00:00
2016-06-20 17:45:33 +00:00
2016-01-26 00:03:25 +00:00
2016-04-08 18:15:37 +00:00
2014-04-25 17:51:25 +00:00
2014-11-17 14:08:57 +00:00
2016-07-25 10:11:00 +00:00
2014-04-03 17:35:22 +00:00
2012-09-29 21:43:49 +00:00
2014-12-04 19:34:50 +00:00
2016-06-16 16:09:53 +00:00
2016-03-31 19:42:04 +00:00
2015-12-17 01:29:08 +00:00
2014-04-03 17:35:22 +00:00
2014-04-03 17:35:22 +00:00
2015-01-19 15:16:06 +00:00
2014-04-23 01:09:29 +00:00
2016-01-26 00:03:25 +00:00
2015-08-13 17:28:16 +00:00