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https://github.com/RPCS3/llvm.git
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f5bddce9ea
This patch adds the PseudoCALLReg instruction which allows using an explicit register operand as the destination for the return address. GCC can successfully parse this form of the call instruction, which would be used for calls to functions which do not use ra as the return address register, such as the __riscv_save libcalls. This patch forms the first part of an implementation of -msave-restore for RISC-V. Differential Revision: https://reviews.llvm.org/D62685 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364403 91177308-0d34-0410-b5e6-96231b3b80d8
469 lines
15 KiB
C++
469 lines
15 KiB
C++
//===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "RISCVGenInstrInfo.inc"
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using namespace llvm;
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RISCVInstrInfo::RISCVInstrInfo()
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: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
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unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case RISCV::LB:
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case RISCV::LBU:
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case RISCV::LH:
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case RISCV::LHU:
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case RISCV::LW:
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case RISCV::FLW:
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case RISCV::LWU:
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case RISCV::LD:
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case RISCV::FLD:
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case RISCV::SB:
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case RISCV::SH:
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case RISCV::SW:
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case RISCV::FSW:
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case RISCV::SD:
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case RISCV::FSD:
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break;
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}
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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return 0;
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}
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void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg,
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unsigned SrcReg, bool KillSrc) const {
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if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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return;
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}
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// FPR->FPR copies
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unsigned Opc;
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if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_S;
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else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_D;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool IsKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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unsigned Opcode;
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
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RISCV::SW : RISCV::SD;
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else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FSW;
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else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FSD;
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else
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llvm_unreachable("Can't store this register to stack slot");
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BuildMI(MBB, I, DL, get(Opcode))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0);
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}
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void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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unsigned Opcode;
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
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RISCV::LW : RISCV::LD;
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else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FLW;
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else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FLD;
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else
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llvm_unreachable("Can't load this register from stack slot");
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BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
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}
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void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag) const {
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assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
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// TODO: If the value can be materialized using only one instruction, only
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// insert a single instruction.
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uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
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uint64_t Lo12 = SignExtend64<12>(Val);
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BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
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.addImm(Hi20)
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.setMIFlag(Flag);
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(DstReg, RegState::Kill)
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.addImm(Lo12)
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.setMIFlag(Flag);
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}
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// The contents of values added to Cond are not examined outside of
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// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
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// push BranchOpcode, Reg1, Reg2.
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static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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Target = LastInst.getOperand(2).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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Cond.push_back(LastInst.getOperand(0));
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Cond.push_back(LastInst.getOperand(1));
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}
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static unsigned getOppositeBranchOpcode(int Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Unrecognized conditional branch");
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case RISCV::BEQ:
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return RISCV::BNE;
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case RISCV::BNE:
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return RISCV::BEQ;
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case RISCV::BLT:
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return RISCV::BGE;
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case RISCV::BGE:
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return RISCV::BLT;
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case RISCV::BLTU:
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return RISCV::BGEU;
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case RISCV::BGEU:
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return RISCV::BLTU;
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}
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}
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bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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Cond.clear();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end() || !isUnpredicatedTerminator(*I))
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return false;
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// Count the number of terminators and find the first unconditional or
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// indirect branch.
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MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
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int NumTerminators = 0;
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for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
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J++) {
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NumTerminators++;
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if (J->getDesc().isUnconditionalBranch() ||
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J->getDesc().isIndirectBranch()) {
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FirstUncondOrIndirectBr = J.getReverse();
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}
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}
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// If AllowModify is true, we can erase any terminators after
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// FirstUncondOrIndirectBR.
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if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
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while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
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std::next(FirstUncondOrIndirectBr)->eraseFromParent();
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NumTerminators--;
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}
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I = FirstUncondOrIndirectBr;
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}
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// We can't handle blocks that end in an indirect branch.
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if (I->getDesc().isIndirectBranch())
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return true;
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// We can't handle blocks with more than 2 terminators.
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if (NumTerminators > 2)
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return true;
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// Handle a single unconditional branch.
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if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
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TBB = I->getOperand(0).getMBB();
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return false;
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}
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// Handle a single conditional branch.
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if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
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parseCondBranch(*I, TBB, Cond);
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return false;
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}
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// Handle a conditional branch followed by an unconditional branch.
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if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
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I->getDesc().isUnconditionalBranch()) {
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parseCondBranch(*std::prev(I), TBB, Cond);
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FBB = I->getOperand(0).getMBB();
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return false;
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}
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// Otherwise, we can't handle this.
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return true;
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}
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unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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if (BytesRemoved)
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*BytesRemoved = 0;
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (!I->getDesc().isUnconditionalBranch() &&
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!I->getDesc().isConditionalBranch())
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!I->getDesc().isConditionalBranch())
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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return 2;
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}
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// Inserts a branch into the end of the specific MachineBasicBlock, returning
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// the number of instructions inserted.
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unsigned RISCVInstrInfo::insertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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if (BytesAdded)
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*BytesAdded = 0;
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 0) &&
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"RISCV branch conditions have two components!");
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// Unconditional branch.
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if (Cond.empty()) {
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MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 1;
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}
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// Either a one or two-way conditional branch.
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unsigned Opc = Cond[0].getImm();
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MachineInstr &CondMI =
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*BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(CondMI);
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// One-way conditional branch.
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if (!FBB)
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return 1;
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// Two-way conditional branch.
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MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 2;
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}
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unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &DestBB,
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const DebugLoc &DL,
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int64_t BrOffset,
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RegScavenger *RS) const {
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assert(RS && "RegScavenger required for long branching");
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assert(MBB.empty() &&
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"new block should be inserted for expanding unconditional branch");
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assert(MBB.pred_size() == 1);
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MachineFunction *MF = MBB.getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
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if (TM.isPositionIndependent())
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report_fatal_error("Unable to insert indirect branch");
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if (!isInt<32>(BrOffset))
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report_fatal_error(
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"Branch offsets outside of the signed 32-bit range not supported");
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// FIXME: A virtual register must be used initially, as the register
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// scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
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// uses the same workaround).
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unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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auto II = MBB.end();
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MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
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.addMBB(&DestBB, RISCVII::MO_HI);
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BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
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.addReg(ScratchReg, RegState::Kill)
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.addMBB(&DestBB, RISCVII::MO_LO);
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RS->enterBasicBlockEnd(MBB);
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unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
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LuiMI.getIterator(), false, 0);
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MRI.replaceRegWith(ScratchReg, Scav);
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MRI.clearVirtRegs();
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RS->setRegUsed(Scav);
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return 8;
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}
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bool RISCVInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 3) && "Invalid branch condition!");
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Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
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return false;
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}
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MachineBasicBlock *
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RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
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assert(MI.getDesc().isBranch() && "Unexpected opcode!");
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// The branch target is always the last operand.
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int NumOp = MI.getNumExplicitOperands();
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return MI.getOperand(NumOp - 1).getMBB();
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}
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bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
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int64_t BrOffset) const {
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// Ideally we could determine the supported branch offset from the
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// RISCVII::FormMask, but this can't be used for Pseudo instructions like
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// PseudoBR.
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switch (BranchOp) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case RISCV::BEQ:
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case RISCV::BNE:
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case RISCV::BLT:
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case RISCV::BGE:
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case RISCV::BLTU:
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case RISCV::BGEU:
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return isIntN(13, BrOffset);
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case RISCV::JAL:
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case RISCV::PseudoBR:
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return isIntN(21, BrOffset);
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}
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}
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unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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default: { return get(Opcode).getSize(); }
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case TargetOpcode::EH_LABEL:
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case TargetOpcode::DBG_VALUE:
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return 0;
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case RISCV::PseudoCALLReg:
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case RISCV::PseudoCALL:
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case RISCV::PseudoTAIL:
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case RISCV::PseudoLLA:
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case RISCV::PseudoLA:
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case RISCV::PseudoLA_TLS_IE:
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case RISCV::PseudoLA_TLS_GD:
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return 8;
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case TargetOpcode::INLINEASM:
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case TargetOpcode::INLINEASM_BR: {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
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return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
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*TM.getMCAsmInfo());
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}
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}
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}
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bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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const unsigned Opcode = MI.getOpcode();
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switch(Opcode) {
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default:
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break;
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case RISCV::ADDI:
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case RISCV::ORI:
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case RISCV::XORI:
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return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
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}
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return MI.isAsCheapAsAMove();
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}
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