mirror of
https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
14e3c54040
This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360768 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
9.8 KiB
LLVM
255 lines
9.8 KiB
LLVM
; RUN: llc -O3 -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s | FileCheck %s
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; RUN: llc -O3 -mtriple=armeb-arm-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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; CHECK-UNSUPPORTED-NOT: smlad
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; CHECK-LABEL: add_user
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; CHECK: %for.body
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; CHECK: ldr [[A:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: ldr [[B:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: sxtah [[COUNT:r[0-9]+]], [[COUNT]], [[A]]
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; CHECK: smlad [[ACC:r[0-9]+]], [[B]], [[A]], [[ACC]]
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define i32 @add_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp24 = icmp sgt i32 %arg, 0
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br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%.pre = load i16, i16* %arg3, align 2
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%.pre27 = load i16, i16* %arg2, align 2
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br label %for.body
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
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%count.final = phi i32 [ 0, %entry ], [ %count.next, %for.body ]
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%res = add i32 %mac1.0.lcssa, %count.final
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ret i32 %res
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for.body:
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%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
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%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
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%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
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%0 = load i16, i16* %arrayidx, align 2
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%add = add nuw nsw i32 %i.025, 1
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%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
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%1 = load i16, i16* %arrayidx1, align 2
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%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
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%2 = load i16, i16* %arrayidx3, align 2
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%conv = sext i16 %2 to i32
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%conv4 = sext i16 %0 to i32
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%count.next = add i32 %conv4, %count
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%mul = mul nsw i32 %conv, %conv4
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%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
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%3 = load i16, i16* %arrayidx6, align 2
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%conv7 = sext i16 %3 to i32
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%conv8 = sext i16 %1 to i32
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%mul9 = mul nsw i32 %conv7, %conv8
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%add10 = add i32 %mul, %mac1.026
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%add11 = add i32 %mul9, %add10
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%exitcond = icmp ne i32 %add, %arg
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br i1 %exitcond, label %for.body, label %for.cond.cleanup
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}
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; CHECK-LABEL: mul_bottom_user
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; CHECK: %for.body
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; CHECK: ldr [[A:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: ldr [[B:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: sxth [[SXT:r[0-9]+]], [[A]]
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; CHECK: smlad [[ACC:r[0-9]+]], [[B]], [[A]], [[ACC]]
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; CHECK: mul [[COUNT:r[0-9]+]],{{.*}}[[SXT]]
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define i32 @mul_bottom_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp24 = icmp sgt i32 %arg, 0
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br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%.pre = load i16, i16* %arg3, align 2
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%.pre27 = load i16, i16* %arg2, align 2
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br label %for.body
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
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%count.final = phi i32 [ 0, %entry ], [ %count.next, %for.body ]
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%res = add i32 %mac1.0.lcssa, %count.final
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ret i32 %res
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for.body:
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%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
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%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
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%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
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%0 = load i16, i16* %arrayidx, align 2
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%add = add nuw nsw i32 %i.025, 1
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%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
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%1 = load i16, i16* %arrayidx1, align 2
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%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
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%2 = load i16, i16* %arrayidx3, align 2
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%conv = sext i16 %2 to i32
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%conv4 = sext i16 %0 to i32
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%mul = mul nsw i32 %conv, %conv4
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%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
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%3 = load i16, i16* %arrayidx6, align 2
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%conv7 = sext i16 %3 to i32
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%conv8 = sext i16 %1 to i32
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%mul9 = mul nsw i32 %conv7, %conv8
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%add10 = add i32 %mul, %mac1.026
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%add11 = add i32 %mul9, %add10
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%count.next = mul i32 %conv4, %count
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%exitcond = icmp ne i32 %add, %arg
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br i1 %exitcond, label %for.body, label %for.cond.cleanup
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}
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; CHECK-LABEL: mul_top_user
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; CHECK: %for.body
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; CHECK: ldr [[A:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: ldr [[B:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: asrs [[ASR:[rl0-9]+]], [[A]], #16
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; CHECK: smlad [[ACC:[rl0-9]+]], [[A]], [[B]], [[ACC]]
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; CHECK: mul [[COUNT:[rl0-9]+]],{{.}}[[ASR]]
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define i32 @mul_top_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp24 = icmp sgt i32 %arg, 0
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br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%.pre = load i16, i16* %arg3, align 2
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%.pre27 = load i16, i16* %arg2, align 2
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br label %for.body
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
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%count.final = phi i32 [ 0, %entry ], [ %count.next, %for.body ]
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%res = add i32 %mac1.0.lcssa, %count.final
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ret i32 %res
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for.body:
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%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
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%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
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%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
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%0 = load i16, i16* %arrayidx, align 2
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%add = add nuw nsw i32 %i.025, 1
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%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
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%1 = load i16, i16* %arrayidx1, align 2
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%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
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%2 = load i16, i16* %arrayidx3, align 2
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%conv = sext i16 %2 to i32
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%conv4 = sext i16 %0 to i32
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%mul = mul nsw i32 %conv, %conv4
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%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
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%3 = load i16, i16* %arrayidx6, align 2
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%conv7 = sext i16 %3 to i32
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%conv8 = sext i16 %1 to i32
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%mul9 = mul nsw i32 %conv7, %conv8
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%add10 = add i32 %mul, %mac1.026
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%add11 = add i32 %mul9, %add10
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%count.next = mul i32 %conv7, %count
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%exitcond = icmp ne i32 %add, %arg
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br i1 %exitcond, label %for.body, label %for.cond.cleanup
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}
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; CHECK-LABEL: and_user
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; CHECK: %for.body
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; CHECK: ldr [[A:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: ldr [[B:[rl0-9]+]],{{.*}}, #2]!
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; CHECK: uxth [[UXT:r[0-9]+]], [[A]]
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; CHECK: smlad [[ACC:r[0-9]+]], [[B]], [[A]], [[ACC]]
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; CHECK: mul [[MUL:r[0-9]+]],{{.*}}[[UXT]]
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define i32 @and_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp24 = icmp sgt i32 %arg, 0
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br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%.pre = load i16, i16* %arg3, align 2
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%.pre27 = load i16, i16* %arg2, align 2
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br label %for.body
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
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%count.final = phi i32 [ 0, %entry ], [ %count.next, %for.body ]
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%res = add i32 %mac1.0.lcssa, %count.final
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ret i32 %res
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for.body:
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%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
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%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
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%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
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%0 = load i16, i16* %arrayidx, align 2
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%add = add nuw nsw i32 %i.025, 1
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%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
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%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
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%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
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%1 = load i16, i16* %arrayidx1, align 2
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%2 = load i16, i16* %arrayidx3, align 2
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%conv = sext i16 %2 to i32
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%conv4 = sext i16 %0 to i32
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%bottom = and i32 %conv4, 65535
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%mul = mul nsw i32 %conv, %conv4
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%3 = load i16, i16* %arrayidx6, align 2
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%conv7 = sext i16 %3 to i32
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%conv8 = sext i16 %1 to i32
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%mul9 = mul nsw i32 %conv7, %conv8
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%add10 = add i32 %mul, %mac1.026
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%add11 = add i32 %mul9, %add10
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%count.next = mul i32 %bottom, %count
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%exitcond = icmp ne i32 %add, %arg
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br i1 %exitcond, label %for.body, label %for.cond.cleanup
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}
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; CHECK-LABEL: multi_uses
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; CHECK: %for.body
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; CHECK: ldr [[A:[rl0-9]+]], [{{.*}}, #2]!
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; CHECK: ldr [[B:[rl0-9]+]], [{{.*}}, #2]!
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; CHECK: sxth [[SXT:r[0-9]+]], [[A]]
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; CHECK: smlad [[ACC:[rl0-9]+]], [[B]], [[A]], [[ACC]]
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; CHECK: eor.w [[EOR:r[0-9]+]], [[SXT]], [[SHIFT:r[0-9]+]]
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; CHECK: muls [[MUL:r[0-9]+]],{{.*}}[[SXT]]
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; CHECK: lsl.w [[SHIFT]], [[MUL]], #16
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define i32 @multi_uses(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp24 = icmp sgt i32 %arg, 0
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br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%.pre = load i16, i16* %arg3, align 2
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%.pre27 = load i16, i16* %arg2, align 2
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br label %for.body
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
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%count.final = phi i32 [ 0, %entry ], [ %count.next, %for.body ]
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%res = add i32 %mac1.0.lcssa, %count.final
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ret i32 %res
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for.body:
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%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
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%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
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%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
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%0 = load i16, i16* %arrayidx, align 2
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%add = add nuw nsw i32 %i.025, 1
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%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
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%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
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%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
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%1 = load i16, i16* %arrayidx1, align 2
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%2 = load i16, i16* %arrayidx3, align 2
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%conv = sext i16 %2 to i32
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%conv4 = sext i16 %0 to i32
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%bottom = and i32 %conv4, 65535
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%mul = mul nsw i32 %conv, %conv4
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%3 = load i16, i16* %arrayidx6, align 2
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%conv7 = sext i16 %3 to i32
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%conv8 = sext i16 %1 to i32
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%mul9 = mul nsw i32 %conv7, %conv8
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%add10 = add i32 %mul, %mac1.026
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%shl = shl i32 %conv4, 16
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%add11 = add i32 %mul9, %add10
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%xor = xor i32 %bottom, %count
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%count.next = mul i32 %xor, %shl
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%exitcond = icmp ne i32 %add, %arg
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br i1 %exitcond, label %for.body, label %for.cond.cleanup
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}
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