Matthias Braun c1fa0731c3 MIRParser: Allow regclass specification on operand ...

You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Differential Revision: https://reviews.llvm.org/D22398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8

2017-01-18 00:59:19 +00:00

..

CMakeLists.txt

[CMake] NFC. Updating CMake dependency specifications

2016-11-17 04:36:50 +00:00

LLVMBuild.txt

MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum().

2015-07-24 01:12:36 +00:00

MILexer.cpp

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

MILexer.h

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

MIParser.cpp

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00

MIParser.h

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00

MIRParser.cpp

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00