Simi Pallipurath 0cf7d296a2 [ARM]Decoding MSR with unpredictable destination register causes an assert ...

This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8

2018-03-06 15:21:19 +00:00

..

ARMDisassembler.cpp

[ARM]Decoding MSR with unpredictable destination register causes an assert

2018-03-06 15:21:19 +00:00

CMakeLists.txt

Cleaning up a bunch of pre-Visual C++ 2012 build hacks.

2014-03-04 09:23:33 +00:00

LLVMBuild.txt

[ARM] Re-commit r324600 with fixed LLVMBuild.txt

2018-02-08 14:31:22 +00:00