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archived-llvm/test/CodeGen/RISCV
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Alex Bradbury 456da09d90 [RISCV] Add test cases for the lp64 ABI 
These are closely modeled on similar tests for the ilp32 ABI. Like those
tests, we group together tests that should be common cross lp64, lp64+lp64f,
and lp64+lp64f+lp64d ABIs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355899 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-12 09:26:53 +00:00
..
addc-adde-sube-subc.ll
[RISCV] Implement frame pointer elimination
2018-01-18 11:34:02 +00:00
align.ll
[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
2018-04-12 11:30:59 +00:00
alloca.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
alu8.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu16.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu32.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
alu64.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
analyze-branch.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
arith-with-overflow.ll
[RISCV] Add tests for overflow intrinsics
2018-06-19 06:45:47 +00:00
atomic-cmpxchg-flag.ll
[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A
2019-03-11 21:41:22 +00:00
atomic-cmpxchg.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
atomic-fence.ll
[RISCV][NFC] Add CHECK lines for atomic operations on RV64I
2019-01-11 19:46:48 +00:00
atomic-load-store.ll
[RISCV] Add codegen support for RV64A
2019-01-17 10:04:39 +00:00
atomic-rmw.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
bare-select.ll
[RISCV] Codegen support for RV32F floating point comparison operations
2018-03-21 15:11:02 +00:00
blockaddress.ll
[RISCV] Peephole optimisation for load/store of global values or constant addresses
2018-03-19 11:54:28 +00:00
branch-relaxation.ll
[RISCV] Implement frame pointer elimination
2018-01-18 11:34:02 +00:00
branch.ll
[RISCV] Expand codegen -> compression sanity checks and move to a single file
2018-04-18 20:17:29 +00:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Set CostPerUse for registers
2018-05-23 21:34:30 +00:00
byval.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Re-organise calling convention tests
2019-02-19 13:47:19 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Re-organise calling convention tests
2019-02-19 13:47:19 +00:00
calling-conv-ilp32.ll
[RISCV] Re-organise calling convention tests
2019-02-19 13:47:19 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Add test cases for the lp64 ABI
2019-03-12 09:26:53 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Add test cases for the lp64 ABI
2019-03-12 09:26:53 +00:00
calling-conv-lp64.ll
[RISCV] Add test cases for the lp64 ABI
2019-03-12 09:26:53 +00:00
calling-conv-rv32f-ilp32.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
calling-conv-sext-zext.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
calls.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
compress-inline-asm.ll
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress.ll
[RISCV] Add test changes missed from rL330293
2018-04-18 20:36:12 +00:00
disable-tail-calls.ll
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
div.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
double-arith.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-bitmanip-dagcombines.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-br-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-calling-conv.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
double-imm.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-intrinsics.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-mem.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-previous-failure.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
double-select-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-stack-spill-restore.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
fixups-diff.ll
[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true
2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
float-arith.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-bitmanip-dagcombines.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-br-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
float-imm.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-intrinsics.ll
[SelectionDAG] Support promotion of the FPOWI integer operand
2019-02-01 03:46:28 +00:00
float-mem.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-select-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
flt-rounds.ll
[SelectionDAG] Support result type promotion for FLT_ROUNDS_
2018-11-30 13:18:33 +00:00
fp128.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
frame.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll
[SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands
2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
hoist-global-addr-base.ll
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
i32-icmp.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
imm-cse.ll
[RISCV] Add imm-cse.ll test case
2018-04-18 20:25:07 +00:00
imm.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
indirectbr.ll
[RISC-V] Fix a test case to not include label names as those aren't
2018-06-21 05:42:05 +00:00
init-array.ll
[RISCV] Use init_array instead of ctors for RISCV target, by default
2018-03-24 18:37:19 +00:00
inline-asm.ll
[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test
2019-02-14 13:09:54 +00:00
interrupt-attr-args-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-ret-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
jumptable.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
large-stack.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
legalize-fneg.ll
[LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types
2019-02-11 22:10:08 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll
[RISCV] Implement isLegalAddImmediate
2018-04-26 13:00:37 +00:00
mem64.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
mem.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
mul.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
musttail-call.ll
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
option-norelax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-norvc.ll
[RISCV] Support .option rvc and norvc assembler directives
2018-05-11 17:30:28 +00:00
option-relax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-rvc.ll
[RISCV] Support .option rvc and norvc assembler directives
2018-05-11 17:30:28 +00:00
pr40333.ll
[RISCV] Custom-legalise 32-bit variable shifts on RV64
2019-01-25 05:04:00 +00:00
prefetch.ll
[SelectionDAG] Support promotion of PREFETCH operands
2018-11-30 10:06:31 +00:00
rem.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
remat.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
rotl-rotr.ll
[RISCV] Implement frame pointer elimination
2018-01-18 11:34:02 +00:00
rv32i-rv64i-float-double.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
rv64d-double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
rv64i-exhaustive-w-insts.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
rv64i-tricky-shifts.ll
[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases
2018-12-01 05:00:00 +00:00
rv64m-exhaustive-w-insts.ll
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
2019-01-25 05:11:34 +00:00
select-cc.ll
[RISCV] Implement frame pointer elimination
2018-01-18 11:34:02 +00:00
sext-zext-trunc.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
shift-masked-shamt.ll
[RISCV] Eliminate unnecessary masking of promoted shift amounts
2018-10-12 23:18:52 +00:00
shifts.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
tail-calls.ll
[RISCV] Fixed test case failure due to r338047
2018-07-31 00:36:28 +00:00
target-abi-invalid.ll
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
target-abi-valid.ll
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
umulo-128-legalisation-lowering.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
vararg.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
wide-mem.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
zext-with-load-is-free.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00