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f41c3c9239
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306514 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.8 KiB
LLVM
60 lines
1.8 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
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define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_weak:
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK-NEXT: BB#0:
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; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK-NEXT: cmp [[LOADED]], r1
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; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#1:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-NEXT: cmp [[SUCCESS]], #0
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; CHECK-NEXT: beq [[SUCCESSBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#2:
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[LDFAILBB]]:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[SUCCESSBB]]:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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store i32 %oldval, i32* %addr
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ret void
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}
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define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_weak_to_bool:
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%success = extractvalue { i32, i1 } %pair, 1
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; CHECK-NEXT: BB#0:
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; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
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; CHECK-NEXT: cmp [[LOADED]], r2
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; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#1:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1]
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; CHECK-NEXT: cmp [[SUCCESS]], #0
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; CHECK-NEXT: bxne lr
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; CHECK-NEXT: mov r0, #1
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[LDFAILBB]]:
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: clrex
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; CHECK-NEXT: bx lr
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ret i1 %success
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}
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