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20f8334c2a
On AMDGPU SGPR spills are really spilled to another register. The spiller creates the spills to new frame index objects, which is used as a placeholder. This will eventually be replaced with a reference to a position in a VGPR to write to and the frame index deleted. It is most likely not a real stack location that can be shared with another stack object. This is a problem when StackSlotColoring decides it should combine a frame index used for a normal VGPR spill with a real stack location and a frame index used for an SGPR. Add an ID field so that StackSlotColoring has a way of knowing the different frame index types are incompatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308673 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.4 KiB
YAML
44 lines
1.4 KiB
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses stack objects correctly.
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--- |
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define i32 @test(i32 %a) #0 {
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entry:
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%b = alloca i32
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%x = alloca i64
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store i32 %a, i32* %b
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store i64 2, i64* %x
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%c = load i32, i32* %b
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ret i32 %c
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}
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attributes #0 = { "no-frame-pointer-elim"="false" }
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...
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---
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name: test
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frameInfo:
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maxAlignment: 8
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# CHECK: stack:
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# CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
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# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
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# CHECK-NEXT: di-location: '' }
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# CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
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# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
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# CHECK-NEXT: di-location: '' }
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# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
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# CHECK-NEXT: di-location: '' }
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stack:
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- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
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- { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
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- { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
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body: |
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bb.0.entry:
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MOV32mr %rsp, 1, _, -4, _, %edi
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MOV64mi32 %rsp, 1, _, -16, _, 2
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%eax = MOV32rm %rsp, 1, _, -4, _
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RETQ %eax
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...
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