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archived-llvm/lib/Target/AMDGPU
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Sanjoy Das b166e6723e (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 
Re-land r321234.  It had to be reverted because it broke the shared
library build.  The shared library build broke because there was a
missing LLVMBuild dependency from lib/Passes (which calls
TargetMachine::getTargetIRAnalysis) to lib/Target.  As far as I can
tell, this problem was always there but was somehow masked
before (perhaps because TargetMachine::getTargetIRAnalysis was a
virtual function).

Original commit message:

This makes the TargetMachine interface a bit simpler.  We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.

See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html

I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.

Reviewers: echristo, MatzeB, hfinkel

Reviewed By: hfinkel

Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D41464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321375 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 18:21:59 +00:00
..
AsmParser
[AMDGPU][MC] Corrected handling of negative expressions
2017-12-22 18:03:35 +00:00
Disassembler
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
2017-12-22 15:18:06 +00:00
InstPrinter
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
2017-12-22 15:18:06 +00:00
MCTargetDesc
[Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
2017-12-13 07:26:17 +00:00
TargetInfo
Add backend name to Target to enable runtime info to be fed back into TableGen
2017-11-15 23:55:44 +00:00
Utils
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
2017-12-22 15:18:06 +00:00
AMDGPU.h
[AMDGPU] Clean up symbols in the global namespace.
2017-10-31 23:21:30 +00:00
AMDGPU.td
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
AMDGPUAliasAnalysis.cpp
[AMDGPU] calling conventions for AMDPAL OS type
2017-09-29 09:51:22 +00:00
AMDGPUAliasAnalysis.h
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Add option to stress calls
2017-09-21 07:00:48 +00:00
AMDGPUAnnotateKernelFeatures.cpp
[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
2017-08-31 21:56:16 +00:00
AMDGPUAnnotateUniformValues.cpp
AMDGPU: Fix converting unanalyzable global loads to SMRD
2017-07-12 23:06:18 +00:00
AMDGPUArgumentUsageInfo.cpp
[CodeGen] Rename functions PrintReg* to printReg*
2017-11-28 12:42:37 +00:00
AMDGPUArgumentUsageInfo.h
[AMDGPU] Fixed MSVC build break
2017-08-04 10:53:07 +00:00
AMDGPUAsmPrinter.cpp
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
2017-12-22 15:18:06 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] add labels to +DumpCode output
2017-12-08 14:09:34 +00:00
AMDGPUCallingConv.td
AMDGPU: Initial implementation of calls
2017-08-01 19:54:18 +00:00
AMDGPUCallLowering.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUCallLowering.h
AMDGPU: Start defining a calling convention
2017-05-17 21:56:25 +00:00
AMDGPUCodeGenPrepare.cpp
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
2017-11-06 16:27:15 +00:00
AMDGPUFrameLowering.cpp
[AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets for SI
2017-03-10 19:39:07 +00:00
AMDGPUFrameLowering.h
Move TargetFrameLowering.h to CodeGen where it's implemented
2017-11-03 22:32:11 +00:00
AMDGPUGenRegisterBankInfo.def
[GlobalISel] Make GlobalISel a non-optional library.
2017-08-03 21:52:25 +00:00
AMDGPUInline.cpp
[AMDGPU] Port of HSAIL inliner
2017-09-20 04:25:58 +00:00
AMDGPUInstrInfo.cpp
AMDGPU: Partially fix disassembly of MIMG instructions
2017-12-13 21:07:51 +00:00
AMDGPUInstrInfo.h
AMDGPU: Partially fix disassembly of MIMG instructions
2017-12-13 21:07:51 +00:00
AMDGPUInstrInfo.td
Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.
2017-10-12 19:37:14 +00:00
AMDGPUInstructions.td
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
AMDGPUInstructionSelector.cpp
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
2017-11-16 00:46:35 +00:00
AMDGPUInstructionSelector.h
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
2017-11-16 00:46:35 +00:00
AMDGPUIntrinsicInfo.cpp
Rename AttributeSet to AttributeList
2017-03-21 16:57:19 +00:00
AMDGPUIntrinsicInfo.h
AMDGPU: Change fdiv lowering based on !fpmath metadata
2016-07-19 23:16:53 +00:00
AMDGPUIntrinsics.td
AMDGPU: Remove legacy bfe intrinsics
2017-04-03 18:08:08 +00:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Fix creating invalid copy when adjusting dmask
2017-12-04 22:18:27 +00:00
AMDGPUISelLowering.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUISelLowering.h
[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.
2017-12-19 19:26:23 +00:00
AMDGPULegalizerInfo.cpp
Fix a bunch more layering of CodeGen headers that are in Target
2017-11-17 01:07:10 +00:00
AMDGPULegalizerInfo.h
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
2017-01-30 21:56:46 +00:00
AMDGPULibCalls.cpp
Make helpers static. NFC.
2017-11-24 14:55:41 +00:00
AMDGPULibFunc.cpp
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
2017-11-04 17:37:43 +00:00
AMDGPULibFunc.h
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
2017-11-04 17:37:43 +00:00
AMDGPULowerIntrinsics.cpp
Extend memcpy expansion in Transform/Utils to handle wider operand types.
2017-07-07 02:00:06 +00:00
AMDGPUMachineCFGStructurizer.cpp
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
AMDGPUMachineFunction.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUMachineFunction.h
Sort the remaining #include lines in include/... and lib/....
2017-06-06 11:49:48 +00:00
AMDGPUMachineModuleInfo.cpp
AMDGPU: Implement memory model
2017-07-21 21:19:23 +00:00
AMDGPUMachineModuleInfo.h
AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
2017-09-07 16:14:21 +00:00
AMDGPUMacroFusion.cpp
AMDGPU: Add macro fusion schedule DAG mutation
2017-07-06 20:57:05 +00:00
AMDGPUMacroFusion.h
AMDGPU: Add macro fusion schedule DAG mutation
2017-07-06 20:57:05 +00:00
AMDGPUMCInstLower.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUMCInstLower.h
Reapply "AMDGPU: Support using tablegened MC pseudo expansions"
2016-10-06 17:19:11 +00:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPU: Fix set but not used warnings related to AMDGPUAS
2017-11-01 19:12:38 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPU: Fix assert on alloca of array of struct
2017-09-14 18:02:29 +00:00
AMDGPUPTNote.h
AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
2017-10-12 18:59:54 +00:00
AMDGPURegAsmNames.inc.cpp
AMDGPU: Work around build special casing .inc files
2017-06-08 19:25:21 +00:00
AMDGPURegisterBankInfo.cpp
Fix a bunch more layering of CodeGen headers that are in Target
2017-11-17 01:07:10 +00:00
AMDGPURegisterBankInfo.h
Sort the remaining #include lines in include/... and lib/....
2017-06-06 11:49:48 +00:00
AMDGPURegisterBanks.td
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
2017-01-30 21:56:46 +00:00
AMDGPURegisterInfo.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPURegisterInfo.h
AMDGPU: Start defining a calling convention
2017-05-17 21:56:25 +00:00
AMDGPURegisterInfo.td
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
2017-07-29 03:44:07 +00:00
AMDGPURewriteOutArguments.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUSubtarget.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUSubtarget.h
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUTargetMachine.cpp
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
2017-12-22 18:21:59 +00:00
AMDGPUTargetMachine.h
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
2017-12-22 18:21:59 +00:00
AMDGPUTargetObjectFile.cpp
AMDGPU: Fix set but not used warnings related to AMDGPUAS
2017-11-01 19:12:38 +00:00
AMDGPUTargetObjectFile.h
[AMDGPU] Get address space mapping by target triple environment
2017-03-27 14:04:01 +00:00
AMDGPUTargetTransformInfo.cpp
LSR: Check more intrinsic pointer operands
2017-12-11 21:38:43 +00:00
AMDGPUTargetTransformInfo.h
LSR: Check more intrinsic pointer operands
2017-12-11 21:38:43 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
2017-10-17 21:27:42 +00:00
AMDGPUUnifyMetadata.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-10 00:46:15 +00:00
AMDILCFGStructurizer.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDKernelCodeT.h
[AMDGPU] Revert r310429 changes in AMDKernelCodeT.h which broke some build bots.
2017-08-09 00:06:29 +00:00
BUFInstructions.td
AMDGPU: Select d16 loads into low component of register
2017-11-13 00:22:09 +00:00
CaymanInstructions.td
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
CMakeLists.txt
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
DSInstructions.td
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
EvergreenInstructions.td
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
FLATInstructions.td
[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
2017-11-27 17:14:35 +00:00
GCNHazardRecognizer.cpp
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
2017-12-07 20:34:25 +00:00
GCNHazardRecognizer.h
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
2017-12-07 20:34:25 +00:00
GCNILPSched.cpp
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
GCNIterativeScheduler.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
GCNIterativeScheduler.h
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
GCNMinRegStrategy.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
GCNProcessors.td
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
GCNRegPressure.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
GCNRegPressure.h
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
GCNSchedStrategy.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
GCNSchedStrategy.h
fix typos in comments and error messges; NFC
2017-07-13 06:48:39 +00:00
LLVMBuild.txt
AMDGPU: Add GlobalISel to required_libraries.
2017-01-28 18:13:08 +00:00
MIMGInstructions.td
AMDGPU: Partially fix disassembly of MIMG instructions
2017-12-13 21:07:51 +00:00
Processors.td
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td
2017-11-10 20:01:58 +00:00
R600ClauseMergePass.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600ControlFlowFinalizer.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600Defines.h
AMDGPU: R600 code splitting cleanup
2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp
Sort the remaining #include lines in include/... and lib/....
2017-06-06 11:49:48 +00:00
R600ExpandSpecialInstrs.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-10 00:46:15 +00:00
R600FrameLowering.cpp
Sort the remaining #include lines in include/... and lib/....
2017-06-06 11:49:48 +00:00
R600FrameLowering.h
AMDGPU: Initial implementation of calls
2017-08-01 19:54:18 +00:00
R600InstrFormats.td
AMDGPU: Remove global isGCN predicates
2017-10-03 00:06:41 +00:00
R600InstrInfo.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600InstrInfo.h
[AMDGPU] Fix pointer info for pseudo source for r600
2017-11-10 01:53:24 +00:00
R600Instructions.td
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
R600Intrinsics.td
AMDGPU: Make intrinsics speculatable
2017-05-02 16:57:44 +00:00
R600ISelLowering.cpp
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
R600ISelLowering.h
Add DAG argument to canMergeStoresTo NFC.
2017-07-10 20:25:54 +00:00
R600MachineFunctionInfo.cpp
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
R600MachineFunctionInfo.h
AMDGPU: Delete more dead code
2016-07-22 17:01:25 +00:00
R600MachineScheduler.cpp
[CodeGen] Rename DEBUG_TYPE to match passnames
2017-07-11 22:08:28 +00:00
R600MachineScheduler.h
[AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
2016-12-09 22:06:55 +00:00
R600OptimizeVectorRegisters.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600Packetizer.cpp
AMDGPU/R600: Initialize more passes
2017-08-02 22:19:45 +00:00
R600Processors.td
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
R600RegisterInfo.cpp
AMDGPU: Start defining a calling convention
2017-05-17 21:56:25 +00:00
R600RegisterInfo.h
AMDGPU: Start defining a calling convention
2017-05-17 21:56:25 +00:00
R600RegisterInfo.td
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
2017-07-29 03:44:07 +00:00
R600Schedule.td
AMDGPU: Fix trailing whitespace
2016-06-10 02:18:02 +00:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 00:47:13 +00:00
SIDebuggerInsertNops.cpp
Sort the remaining #include lines in include/... and lib/....
2017-06-06 11:49:48 +00:00
SIDefines.h
[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
2017-12-11 15:23:20 +00:00
SIFixSGPRCopies.cpp
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
SIFixVGPRCopies.cpp
[AMDGPU] Add VGPR copies post regalloc fix pass
2017-01-24 17:46:17 +00:00
SIFixWWMLiveness.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIFoldOperands.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIFrameLowering.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIFrameLowering.h
[AMDGPU] AMDPAL scratch buffer support
2017-09-29 09:49:35 +00:00
SIInsertSkips.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output."
2017-12-07 21:14:41 +00:00
SIInsertWaits.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 00:47:13 +00:00
SIInstrFormats.td
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
SIInstrInfo.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIInstrInfo.h
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
SIInstrInfo.td
AMDGPU: Fix creating invalid copy when adjusting dmask
2017-12-04 22:18:27 +00:00
SIInstructions.td
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
SIIntrinsics.td
AMDGPU: Remove legacy export intrinsic
2017-04-04 16:34:39 +00:00
SIISelLowering.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIISelLowering.h
TLI: Allow using PSV for intrinsic mem operands
2017-12-14 22:34:10 +00:00
SILoadStoreOptimizer.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SILowerControlFlow.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SILowerI1Copies.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIMachineFunctionInfo.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIMachineFunctionInfo.h
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
2017-11-08 01:01:31 +00:00
SIMachineScheduler.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIMachineScheduler.h
AMDGPU/SI: Force exports at the end for SI scheduler
2017-07-25 20:36:58 +00:00
SIMemoryLegalizer.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIOptimizeExecMasking.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIOptimizeExecMaskingPreRA.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIPeepholeSDWA.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIRegisterInfo.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIRegisterInfo.h
[SystemZ] implement shouldCoalesce()
2017-09-29 14:31:39 +00:00
SIRegisterInfo.td
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
2017-12-22 15:18:06 +00:00
SISchedule.td
AMDGPU: Implement early ifcvt target hooks.
2017-01-25 04:25:02 +00:00
SIShrinkInstructions.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIWholeQuadMode.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SMInstructions.td
AMDGPU: Set IntrReadMem on memtime intrinsics
2017-12-08 20:01:02 +00:00
SOPInstructions.td
AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
2017-10-24 10:26:59 +00:00
VIInstrFormats.td
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
2016-09-23 09:08:07 +00:00
VIInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VOP1Instructions.td
AMDGPU: Remove global isGCN predicates
2017-10-03 00:06:41 +00:00
VOP2Instructions.td
[AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32
2017-11-29 13:33:40 +00:00
VOP3Instructions.td
[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
2017-11-24 15:37:14 +00:00
VOP3PInstructions.td
AMDGPU: Add max-mix-insts subtarget feature
2017-10-25 07:00:51 +00:00
VOPCInstructions.td
AMDGPU: Remove global isGCN predicates
2017-10-03 00:06:41 +00:00
VOPInstructions.td
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
2017-11-17 15:15:40 +00:00