Amaury Sechet 3e8866efa2 Remove SETCCE use from Lanai's backend ...

Summary: This creates a small perf regression, but after talking with Jacques Pienaar, he was good with it to get things moving toward removng SETCCE.

Reviewers: jpienaar, bryant

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333838 91177308-0d34-0410-b5e6-96231b3b80d8

2018-06-03 12:56:24 +00:00

..

codemodel.ll

[lanai] Simplify small section check in LowerGlobalAddress and treat ldata sections specially.

2016-12-15 16:56:16 +00:00

comparisons_i32.ll

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comparisons_i64.ll

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

constant_multiply.ll

[lanai] Manually match 0/-1 with R0/R1.

2016-11-29 23:01:09 +00:00

delay_filler.ll

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i32.ll

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lanai-misched-trivial-disjoint.ll

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

lit.local.cfg

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lshift64.ll

[lanai] Custom lowering of SHL_PARTS

2016-12-02 22:01:28 +00:00

masking_setccs.ll

[lanai] Add computeKnownBitsForTargetNode for Lanai.

2017-05-09 18:35:26 +00:00

mem_alu_combiner.ll

[lanai] Change reloc to use PIC_ by default and cleanup.

2016-05-20 21:41:53 +00:00

multiply.ll

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peephole-compare.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

rshift64.ll

[lanai] Add custom lowering for SRL_PARTS i32.

2016-04-14 17:59:22 +00:00

select.ll

[lanai] Add lowering for SETCCE i32.

2016-04-19 19:15:25 +00:00

set_and_hi.ll

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shift.ll

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stack-frame.ll

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sub-cmp-peephole.ll

[lanai] Use peephole optimizer to generate more conditional ALU operations.

2016-07-07 23:36:04 +00:00

subword.ll

[lanai] Add subword scheduling itineraries.

2016-04-20 18:28:55 +00:00