RPCS3/archived-rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2026-01-31 01:25:18 +01:00
Code Issues Packages Projects Releases Wiki Activity
18,703 Commits 6 Branches 74 Tags
eaebd3426e7050c35beb8f24952d6da4d6a75360
Commit Graph

48 Commits

Author SHA1 Message Date
Malcolm
eaebd3426e LLVM: enable FMA for ARM cpus unconditionally 
- All armv8 machines should have FMA.
- Should be a speedup for snapdragon elite and apple machines.
 2026-01-15 08:29:33 +02:00
Niram7777
8c9d266284 Build LLVM wrap getFirstNonPHI by version 2025-12-19 13:40:04 +00:00
Marin Baron
46db5c35eb Build LLVM deprecated getFirstNonPHI 2025-12-19 13:40:04 +00:00
Yahfz
7fe3afbbc2 Add support for arrowlake-s and lunarlake CPUs 2025-07-20 03:27:47 +03:00
Yahfz
8b9c9f677a ARL wasn't using FMA/VNNI/GFNI 2025-07-20 01:18:21 +03:00
RipleyTom
cd87a64621 Headers cleanup 2025-02-11 20:38:35 +01:00
Elad
b073d08a52 LLVM: Implement Recursive Intrinsics 2024-11-23 20:22:58 +02:00
kd-11
4da30e9eca Add proper transform pass management 2024-08-24 14:13:14 +03:00
kd-11
a976ac3353 jit: Add aarch64 JIT backend for pre-codegen transforms 2024-08-08 13:40:07 +03:00
kd-11
3e7c1e207d Add fallback CPU detection when llvm is not aware of the CPU model 2024-08-03 21:35:10 +03:00
oltolm
c567c92d4b fix GCC warnings 2024-03-28 08:45:20 +01:00
Malcolm Jestadt
d1bea790f3 SPU LLVM: Optimize GB/GBH/GBB with a GFNI path 
- Abuses GFNI to extract bits from bytes, from 5->2 instructions in most cases
 2023-10-01 23:05:28 +03:00
Ivan Chikish
06b0e35fb9 Update to LLVM 16.0.1 
Fix Zen4+ AVX-512 detection
 2023-04-11 12:13:09 +03:00
Ivan Chikish
fb88e1c1c9 Update to LLVM 16.0.0, switch to upstream LLVM 2023-04-06 10:19:31 +03:00
oltolm
520524285a llvm: update code to new API (#13500) 
* llvm: update code to new API

* llvm: remove OLDLLVM define
 2023-03-11 01:57:21 +03:00
sguo35
84a785ea67 arm64: implement pshufb intrinsic 2022-08-05 22:53:11 +02:00
sguo35
b02e6e222f arm64: enable fma and "avx" on Apple and Cortex CPUs 2022-07-15 12:37:33 +03:00
Elad Ashkenazi
004d9b09b8 LLVM: Fix 0 vector constant observation 2022-06-08 19:31:39 +03:00
Nekotekina
580bd2b25e Initial Linux Aarch64 support 
* Update asmjit dependency (aarch64 branch)
* Disable USE_DISCORD_RPC by default
* Dump some JIT objects in rpcs3 cache dir
* Add SIGILL handler for all platforms
* Fix resetting zeroing denormals in thread pool
* Refactor most v128:: utils into global gv_** functions
* Refactor PPU interpreter (incomplete), remove "precise"
* - Instruction specializations with multiple accuracy flags
* - Adjust calling convention for speed
* - Removed precise/fast setting, replaced with static
* - Started refactoring interpreters for building at runtime JIT
*   (I got tired of poor compiler optimizations)
* - Expose some accuracy settings (SAT, NJ, VNAN, FPCC)
* - Add exec_bytes PPU thread variable (akin to cycle count)
* PPU LLVM: fix VCTUXS+VCTSXS instruction NaN results
* SPU interpreter: remove "precise" for now (extremely non-portable)
* - As with PPU, settings changed to static/dynamic for interpreters.
* - Precise options will be implemented later
* Fix termination after fatal error dialog
 2022-01-15 06:48:04 +03:00
Nekotekina
6730dc1dc4 LLVM DSL: print some debug info in get_const_vector<v128> 2021-12-07 13:21:24 +03:00
Malcolm Jestadt
7573d7289b SPU LLVM: Hook up 128 bit spu verification 
- Also fix FMA enablement for sapphirerapids
 2021-11-06 21:12:12 +03:00
Ani
1a0392bf15 CPUTranslator: Enable FMA for alderlake CPUs (#11106) 2021-11-03 19:31:46 +00:00
Nekotekina
69f321a471 LLVM 13 2021-11-02 20:11:08 +03:00
Nekotekina
d28b0ba2fa SPU LLVM: implement spu_re, spu_rsqrte 
Improve matching with peek_through_bitcasts() helper.
Implement erase_stores() helper.
 2021-09-17 10:23:43 +03:00
Nekotekina
4b8ee85995 LLVM DSL: reimplement pshufb, add 'calli' 
Implement postponed custom intrinsic replacement.
Make bitcast operator static like other ones.
 2021-09-17 10:23:43 +03:00
Nekotekina
7cf9d1380b LLVM DSL: add line number in get_const_vector automatically 2021-09-17 10:23:43 +03:00
Malcolm Jestadt
43cc62d267 SPU LLVM: Add m_use_vnni 
- Alderlake and Sapphirerapids will require an update to the llvm fork before they can be detected
 2021-08-31 14:02:05 +03:00
Paul
4e12e70929 Add Intel's Rocket Lake 11th gen cpu. (#10205) 
This does nothing but may be required later.
 2021-05-13 11:34:37 +03:00
Malcolm Jestadt
0a7df9d02e SPU LLVM: add AVX-512 SPU verification 
- This is hidden behind a new setting, as some cpus may downclock agressively when executing 512 wide instructions
 2021-04-16 09:35:26 +03:00
Megamouse
a16d8ba3ea More random changes 2021-04-11 14:01:51 +03:00
Nekotekina
35322b5d14 Remove deprecated _bit accessor from v128 
Complicated (a lot of code), confusing (ambiguous)
 2020-12-29 21:04:28 +03:00
Nekotekina
bd269bccaf types.hpp: remove intrinsic includes 
Replace v128 with u128 in some places.
Removed some unused files.
 2020-12-21 21:11:25 +03:00
Nekotekina
36c8654fb8 Remove HERE macro 
Some cleanup.
Add location to some functions.
 2020-12-10 12:30:22 +03:00
Nekotekina
e055d16b2c Replace verify() with ensure() with auto src location. 
Expression ensure(x) returns x.
Using comma operator removed.
 2020-12-09 15:43:38 +03:00
RipleyTom
af8c661a64 Remove BOM markers 2020-12-06 15:30:12 +03:00
Nekotekina
1b8bf081b5 Upgrade to LLVM 11 Stable 2020-11-02 21:23:25 +03:00
Whatcookie
4ce2ad54a8 PPU LLVM: Use VPERM2B to emulate VPERM (#8704) 
- The VPERM2B instructions are a match of VPERM's behavior, besides operating in reverse byte order
 2020-08-09 01:50:26 +01:00
Eladash
f6764767f6 SPU/PPU LLVM: Fix cpu_translator::get_const_vector<v128>() 2020-07-30 17:06:24 +01:00
Nekotekina
e1042bc631 Get rid of "module" keyword 
Workaround some intellisense problems.
 2020-05-06 18:20:11 +03:00
Nekotekina Aux1
250736ece5 Fix warnings in emucore 2020-03-04 21:23:34 +03:00
Eladash
8762f2a588 Use more starts_with 2020-02-29 13:06:14 +03:00
Nekotekina
068450d4fe CPUTranslator: detect FMA feature 2019-12-20 21:11:07 +03:00
Nekotekina
377e7d2a73 C-style cast cleanup VI 2019-12-04 17:56:22 +03:00
Nekotekina
7492f335e9 SPU analyser: basic function detection in Giga mode 
Misc: fix EH frame registration (LLVM, non-Windows).
Misc: constant-folding bitcast (cpu_translator).
Misc: add syntax for LLVM arrays (cpu_translator).
Misc: use function names for proper linkage (SPU LLVM).

Changed function search and verification in Giga mode.
Basic stack frame layout analysis.
Function detection in Giga mode.
Basic use of new information in SPU LLVM.
Fixed jump table compilation in SPU LLVM.
Disable broken optimization in Accurate xfloat mode.
Make compiled SPU modules position-independent in SPU LLVM.

Optimizations include but not limited to:
 * Compiling SPU functions as native functions when eligible
 * Avoiding register context write-out
 * Aligned stack assumption (CWD alike instruction)
 2019-05-11 02:13:19 +03:00
Nekotekina
88d0316aad Update cpu_translator 
Add get_const_vector<v128>()
Add make_const_vector<v128>()
Add i2 and i4 types
Add build<>() for vector constants
Fix comparisons, allow EQ/NE for bool/char/i2/i4 types
 2018-07-05 22:26:35 +03:00
Nekotekina
8b704588d0 Update cpu_translator 2018-05-08 13:05:29 +03:00
Nekotekina
db83113316 Initial cpu_translator impl 2018-02-08 21:10:03 +03:00
Nekotekina
a8bebcba55 LLVM AOT 2016-06-19 21:29:48 +03:00