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Added missing baseReg() and indexReg() to arm::Mem operand

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This commit is contained in:
kobalicek 2022-02-24 22:39:07 +01:00
parent a4e1e88374
commit 6efd4d563d
1 changed files with 52 additions and 27 deletions
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79
src/asmjit/arm/armoperand.h
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@ -455,11 +455,12 @@ public:
//! \} //! \}
//! \name ARM Specific Features //! \name Clone
//! \{ //! \{
//! Clones the memory operand. //! Clones the memory operand.
inline constexpr Mem clone() const noexcept { return Mem(*this); } inline constexpr Mem clone() const noexcept { return Mem(*this); }
//! Gets new memory operand adjusted by `off`. //! Gets new memory operand adjusted by `off`.
inline Mem cloneAdjusted(int64_t off) const noexcept { inline Mem cloneAdjusted(int64_t off) const noexcept {
Mem result(*this); Mem result(*this);
@ -467,6 +468,51 @@ public:
return result; return result;
} }
//! Clones the memory operand and makes it pre-index.
inline Mem pre() const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
return result;
}
//! Clones the memory operand, applies a given offset `off` and makes it pre-index.
inline Mem pre(int64_t off) const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
result.addOffset(off);
return result;
}
//! Clones the memory operand and makes it post-index.
inline Mem post() const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
return result;
}
//! Clones the memory operand, applies a given offset `off` and makes it post-index.
inline Mem post(int64_t off) const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPostIndex);
result.addOffset(off);
return result;
}
//! \}
//! \name Base & Index
//! \{
//! Converts memory `baseType` and `baseId` to `arm::Reg` instance.
//!
//! The memory must have a valid base register otherwise the result will be wrong.
inline Reg baseReg() const noexcept { return Reg::fromTypeAndId(baseType(), baseId()); }
//! Converts memory `indexType` and `indexId` to `arm::Reg` instance.
//!
//! The memory must have a valid index register otherwise the result will be wrong.
inline Reg indexReg() const noexcept { return Reg::fromTypeAndId(indexType(), indexId()); }
using BaseMem::setIndex; using BaseMem::setIndex;
inline void setIndex(const BaseReg& index, uint32_t shift) noexcept { inline void setIndex(const BaseReg& index, uint32_t shift) noexcept {
@ -474,6 +520,11 @@ public:
setShift(shift); setShift(shift);
} }
//! \}
//! \name ARM Specific Features
//! \{
//! Gets whether the memory operand has shift (aka scale) constant. //! Gets whether the memory operand has shift (aka scale) constant.
inline constexpr bool hasShift() const noexcept { return _signature.hasField<kSignatureMemShiftValueMask>(); } inline constexpr bool hasShift() const noexcept { return _signature.hasField<kSignatureMemShiftValueMask>(); }
//! Gets the memory operand's shift (aka scale) constant. //! Gets the memory operand's shift (aka scale) constant.
@ -499,32 +550,6 @@ public:
inline void makePreIndex() noexcept { setPredicate(kOffsetPreIndex); } inline void makePreIndex() noexcept { setPredicate(kOffsetPreIndex); }
inline void makePostIndex() noexcept { setPredicate(kOffsetPostIndex); } inline void makePostIndex() noexcept { setPredicate(kOffsetPostIndex); }
inline Mem pre() const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
return result;
}
inline Mem pre(int64_t off) const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
result.addOffset(off);
return result;
}
inline Mem post() const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPreIndex);
return result;
}
inline Mem post(int64_t off) const noexcept {
Mem result(*this);
result.setPredicate(kOffsetPostIndex);
result.addOffset(off);
return result;
}
//! \} //! \}
}; };