llvm-mirror/utils/TableGen/CodeGenInstruction.h

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//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines a wrapper class for the 'Instruction' TableGen class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
#define LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/SMLoc.h"
#include <string>
#include <utility>
#include <vector>
namespace llvm {
template <typename T> class ArrayRef;
class Record;
class DagInit;
class CodeGenTarget;
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class CGIOperandList {
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public:
class ConstraintInfo {
enum { None, EarlyClobber, Tied } Kind;
unsigned OtherTiedOperand;
public:
ConstraintInfo() : Kind(None) {}
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static ConstraintInfo getEarlyClobber() {
ConstraintInfo I;
I.Kind = EarlyClobber;
I.OtherTiedOperand = 0;
return I;
}
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static ConstraintInfo getTied(unsigned Op) {
ConstraintInfo I;
I.Kind = Tied;
I.OtherTiedOperand = Op;
return I;
}
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bool isNone() const { return Kind == None; }
bool isEarlyClobber() const { return Kind == EarlyClobber; }
bool isTied() const { return Kind == Tied; }
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unsigned getTiedOperand() const {
assert(isTied());
return OtherTiedOperand;
}
bool operator==(const ConstraintInfo &RHS) const {
if (Kind != RHS.Kind)
return false;
if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
return false;
return true;
}
bool operator!=(const ConstraintInfo &RHS) const {
return !(*this == RHS);
}
};
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/// OperandInfo - The information we keep track of for each operand in the
/// operand list for a tablegen instruction.
struct OperandInfo {
/// Rec - The definition this operand is declared as.
///
Record *Rec;
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/// Name - If this operand was assigned a symbolic name, this is it,
/// otherwise, it's empty.
std::string Name;
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/// PrinterMethodName - The method used to print operands of this type in
/// the asmprinter.
std::string PrinterMethodName;
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/// EncoderMethodName - The method used to get the machine operand value
/// for binary encoding. "getMachineOpValue" by default.
std::string EncoderMethodName;
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/// OperandType - A value from MCOI::OperandType representing the type of
/// the operand.
std::string OperandType;
/// MIOperandNo - Currently (this is meant to be phased out), some logical
/// operands correspond to multiple MachineInstr operands. In the X86
/// target for example, one address operand is represented as 4
/// MachineOperands. Because of this, the operand number in the
/// OperandList may not match the MachineInstr operand num. Until it
/// does, this contains the MI operand index of this operand.
unsigned MIOperandNo;
unsigned MINumOperands; // The number of operands.
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/// DoNotEncode - Bools are set to true in this vector for each operand in
/// the DisableEncoding list. These should not be emitted by the code
/// emitter.
std::vector<bool> DoNotEncode;
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/// MIOperandInfo - Default MI operand type. Note an operand may be made
/// up of multiple MI operands.
DagInit *MIOperandInfo;
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/// Constraint info for this operand. This operand can have pieces, so we
/// track constraint info for each.
std::vector<ConstraintInfo> Constraints;
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OperandInfo(Record *R, const std::string &N, const std::string &PMN,
const std::string &EMN, const std::string &OT, unsigned MION,
unsigned MINO, DagInit *MIOI)
: Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN),
OperandType(OT), MIOperandNo(MION), MINumOperands(MINO),
MIOperandInfo(MIOI) {}
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/// getTiedOperand - If this operand is tied to another one, return the
/// other operand number. Otherwise, return -1.
int getTiedRegister() const {
for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
const CGIOperandList::ConstraintInfo &CI = Constraints[j];
if (CI.isTied()) return CI.getTiedOperand();
}
return -1;
}
};
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CGIOperandList(Record *D);
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Record *TheDef; // The actual record containing this OperandList.
/// NumDefs - Number of def operands declared, this is the number of
/// elements in the instruction's (outs) list.
///
unsigned NumDefs;
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/// OperandList - The list of declared operands, along with their declared
/// type (which is a record).
std::vector<OperandInfo> OperandList;
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// Information gleaned from the operand list.
bool isPredicable;
bool hasOptionalDef;
bool isVariadic;
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// Provide transparent accessors to the operand list.
bool empty() const { return OperandList.empty(); }
unsigned size() const { return OperandList.size(); }
const OperandInfo &operator[](unsigned i) const { return OperandList[i]; }
OperandInfo &operator[](unsigned i) { return OperandList[i]; }
OperandInfo &back() { return OperandList.back(); }
const OperandInfo &back() const { return OperandList.back(); }
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typedef std::vector<OperandInfo>::iterator iterator;
typedef std::vector<OperandInfo>::const_iterator const_iterator;
iterator begin() { return OperandList.begin(); }
const_iterator begin() const { return OperandList.begin(); }
iterator end() { return OperandList.end(); }
const_iterator end() const { return OperandList.end(); }
/// getOperandNamed - Return the index of the operand with the specified
/// non-empty name. If the instruction does not have an operand with the
/// specified name, abort.
unsigned getOperandNamed(StringRef Name) const;
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/// hasOperandNamed - Query whether the instruction has an operand of the
/// given name. If so, return true and set OpIdx to the index of the
/// operand. Otherwise, return false.
bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
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/// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
/// where $foo is a whole operand and $foo.bar refers to a suboperand.
/// This aborts if the name is invalid. If AllowWholeOp is true, references
/// to operands with suboperands are allowed, otherwise not.
std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
bool AllowWholeOp = true);
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/// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
/// flat machineinstr operand #.
unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
return OperandList[Op.first].MIOperandNo + Op.second;
}
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/// getSubOperandNumber - Unflatten a operand number into an
/// operand/suboperand pair.
std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
for (unsigned i = 0; ; ++i) {
assert(i < OperandList.size() && "Invalid flat operand #");
if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
return std::make_pair(i, Op-OperandList[i].MIOperandNo);
}
}
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/// isFlatOperandNotEmitted - Return true if the specified flat operand #
/// should not be emitted with the code emitter.
bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
if (OperandList[Op.first].DoNotEncode.size() > Op.second)
return OperandList[Op.first].DoNotEncode[Op.second];
return false;
}
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void ProcessDisableEncoding(std::string Value);
};
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class CodeGenInstruction {
public:
Record *TheDef; // The actual record defining this instruction.
StringRef Namespace; // The namespace the instruction is in.
/// AsmString - The format string used to emit a .s file for the
/// instruction.
std::string AsmString;
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/// Operands - This is information about the (ins) and (outs) list specified
/// to the instruction.
CGIOperandList Operands;
/// ImplicitDefs/ImplicitUses - These are lists of registers that are
/// implicitly defined and used by the instruction.
std::vector<Record*> ImplicitDefs, ImplicitUses;
// Various boolean values we track for the instruction.
bool isReturn : 1;
bool isEHScopeReturn : 1;
bool isBranch : 1;
bool isIndirectBranch : 1;
bool isCompare : 1;
bool isMoveImm : 1;
bool isMoveReg : 1;
bool isBitcast : 1;
bool isSelect : 1;
bool isBarrier : 1;
bool isCall : 1;
bool isAdd : 1;
bool isTrap : 1;
bool canFoldAsLoad : 1;
bool mayLoad : 1;
bool mayLoad_Unset : 1;
bool mayStore : 1;
bool mayStore_Unset : 1;
bool isPredicable : 1;
bool isConvertibleToThreeAddress : 1;
bool isCommutable : 1;
bool isTerminator : 1;
bool isReMaterializable : 1;
bool hasDelaySlot : 1;
bool usesCustomInserter : 1;
bool hasPostISelHook : 1;
bool hasCtrlDep : 1;
bool isNotDuplicable : 1;
bool hasSideEffects : 1;
bool hasSideEffects_Unset : 1;
bool isAsCheapAsAMove : 1;
bool hasExtraSrcRegAllocReq : 1;
bool hasExtraDefRegAllocReq : 1;
bool isCodeGenOnly : 1;
bool isPseudo : 1;
bool isRegSequence : 1;
bool isExtractSubreg : 1;
bool isInsertSubreg : 1;
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
[TableGen] Support multi-alternative pattern fragments A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999
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bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;
/// Are there any undefined flags?
bool hasUndefFlags() const {
return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
}
// The record used to infer instruction flags, or NULL if no flag values
// have been inferred.
Record *InferredFrom;
CodeGenInstruction(Record *R);
/// HasOneImplicitDefWithKnownVT - If the instruction has at least one
/// implicit def and it has a known VT, return the VT, otherwise return
/// MVT::Other.
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MVT::SimpleValueType
HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
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/// FlattenAsmStringVariants - Flatten the specified AsmString to only
/// include text from the specified variant, returning the new string.
static std::string FlattenAsmStringVariants(StringRef AsmString,
unsigned Variant);
// Is the specified operand in a generic instruction implicitly a pointer.
// This can be used on intructions that use typeN or ptypeN to identify
// operands that should be considered as pointers even though SelectionDAG
// didn't make a distinction between integer and pointers.
bool isOperandAPointer(unsigned i) const;
};
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/// CodeGenInstAlias - This represents an InstAlias definition.
class CodeGenInstAlias {
public:
Record *TheDef; // The actual record defining this InstAlias.
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/// AsmString - The format string used to emit a .s file for the
/// instruction.
std::string AsmString;
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/// Result - The result instruction.
DagInit *Result;
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/// ResultInst - The instruction generated by the alias (decoded from
/// Result).
CodeGenInstruction *ResultInst;
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struct ResultOperand {
private:
std::string Name;
Record *R;
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int64_t Imm;
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public:
enum {
K_Record,
K_Imm,
K_Reg
} Kind;
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ResultOperand(std::string N, Record *r)
: Name(std::move(N)), R(r), Kind(K_Record) {}
ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
ResultOperand(Record *r) : R(r), Kind(K_Reg) {}
bool isRecord() const { return Kind == K_Record; }
bool isImm() const { return Kind == K_Imm; }
bool isReg() const { return Kind == K_Reg; }
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StringRef getName() const { assert(isRecord()); return Name; }
Record *getRecord() const { assert(isRecord()); return R; }
int64_t getImm() const { assert(isImm()); return Imm; }
Record *getRegister() const { assert(isReg()); return R; }
unsigned getMINumOperands() const;
};
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/// ResultOperands - The decoded operands for the result instruction.
std::vector<ResultOperand> ResultOperands;
/// ResultInstOperandIndex - For each operand, this vector holds a pair of
/// indices to identify the corresponding operand in the result
/// instruction. The first index specifies the operand and the second
/// index specifies the suboperand. If there are no suboperands or if all
/// of them are matched by the operand, the second value should be -1.
std::vector<std::pair<unsigned, int> > ResultInstOperandIndex;
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CodeGenInstAlias(Record *R, CodeGenTarget &T);
bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
Record *InstOpRec, bool hasSubOps, ArrayRef<SMLoc> Loc,
CodeGenTarget &T, ResultOperand &ResOp);
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};
}
#endif