diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 05797c81ab9..df9164a07a3 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -45,7 +45,6 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); - addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass); addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); if (!UseSoftFloat) { diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 7bfd8eb82bd..9b98ec71198 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -810,18 +810,18 @@ def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; // muls def : Pat<(mulhs GR32:$src1, GR32:$src2), - (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GR32:$src1, subreg_odd32), GR32:$src2), subreg_even32)>; def : Pat<(mulhu GR32:$src1, GR32:$src2), - (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GR32:$src1, subreg_odd32), GR32:$src2), subreg_even32)>; def : Pat<(mulhu GR64:$src1, GR64:$src2), - (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src1, subreg_odd), GR64:$src2), subreg_even)>; diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index 73df94238b2..8795847a6c3 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -399,7 +399,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64, }]; } -def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128, +def GR128 : RegisterClass<"SystemZ", [v2i64], 128, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> { let SubRegClassList = [GR32, GR32, GR64, GR64];