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Out GR128 regclass is not a 'real' i128 one.
llvm-svn: 76044
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@ -45,7 +45,6 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
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addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
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addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
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if (!UseSoftFloat) {
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@ -810,18 +810,18 @@ def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
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// muls
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def : Pat<(mulhs GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd32),
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GR32:$src2),
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subreg_even32)>;
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def : Pat<(mulhu GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd32),
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GR32:$src2),
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subreg_even32)>;
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def : Pat<(mulhu GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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@ -399,7 +399,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
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}];
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}
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def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128,
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def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
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[R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
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{
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let SubRegClassList = [GR32, GR32, GR64, GR64];
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