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Fix a typo in AMDGPU docs
Reviewers: t-tye, arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81247
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@ -3851,7 +3851,7 @@ The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
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4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
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or (X, Y, Z).
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Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64-bit
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Flat Scratch register pair are adjacent SGPRs so they can be moved as a 64-bit
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value to the hardware required SGPRn-3 and SGPRn-4 respectively.
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The global segment can be accessed either using buffer instructions (GFX6 which
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