Fix a typo in AMDGPU docs

Reviewers: t-tye, arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81247
This commit is contained in:
madhur13490 2020-05-07 17:27:32 +00:00
parent 7209d63282
commit 1759a48fb7

View File

@ -3851,7 +3851,7 @@ The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
or (X, Y, Z).
Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64-bit
Flat Scratch register pair are adjacent SGPRs so they can be moved as a 64-bit
value to the hardware required SGPRn-3 and SGPRn-4 respectively.
The global segment can be accessed either using buffer instructions (GFX6 which